Xilinx —Oasys deal for chip synthesis tech

SAN FRANCISCO: Xilinx Inc, the leading programmable logic vendor has signed a multi-year strategic licensing agreement with EDA vendor Oasys Design Systems to use chip synthesis technology.

A report cited Vin Ratford, senior vice President of world wide marketing, Xilinx as saying it is necessary to generate new synthesis to support the needs of the customers, since the programming chips were growing more and more complex these days. The details of the agreement for implementing the technologies in FPGAs has not being disclosed.

Oasys Design Systems is a new venture which has managed a steady growth over the past four years. Last year, the company introduced a new design tool called RealTime Designer, for physical RTL synthesis of 100-million-gate designs. The same technology of the tool is used here for Xilinx.

According to Oasys President and CEO Paul van Besouw, the company would continue to focus on providing tools for ASIC designers. The partnership with Xilinx would bring the benefits of the company's technology to leading edge FPGA designers as well, he said.