Xilinx expands FEC IP core for better network

BANGALORE, INDIA: To include GFEC eFEC and high gain FEC (xFEC) solutions, Xilinx expanded its Forward Error Correction (FEC) IP core. These solutions are used to obtain error control in signal transmission and extend the distance of a transmission that reduces the number of regenerators (hops) along the route, which reduces OpEx and CapEx costs for network operators.

FEC IP cores have been designed with a common interface to accelerate product development, minimise system level integration time, maximise design reuse and reduce time to market.

The ultra-compact, high-performance FEC cores were designed internally and optimised specifically for Xilinx FPGAs to occupy less silicon real estate than non-Xilinx IP cores, making them the smallest FEC cores available. The FEC cores include GFEC IP cores for 2.5G, 10G, 40G and 100G applications , legacy 10G eFECs and a Xilinx Extended FEC (xFEC) IP core for 100G applications.

The company is also planning to add 400G GFEC for leading edge applications. It will be available in Q2 2013. Combined with partial reconfiguration, these IP cores optimised for Xilinx FPGAs enable customers to integrate multiple FEC standards on multiple interfaces. As per Xilinx, it reduces product costs, power consumption and maximise network interoperability.

"As bandwidth demands increase and the tolerance for errors and latency decreases, system designers are looking for new ways to expand available bandwidth and improve the quality of transmission. To solve these challenges, Xilinx has extended our leadership position in the OTN marketplace by delivering this expanded offering of FEC IP cores for 2.5G, 10G, 40G ,100G and 400G applications. The power/performance available in our 7 series FPGA family combined with this FEC portfolio enables our customers to achieve higher data rates, increase bandwidth and reduce system costs within the OTN application space,” said Nick Possley, Senior Director, wired communications, Xilinx.

Different FEC schemes provide different levels of coding gain. The higher the coding gain, the greater the distance an optical signal can be transmitted. The coding gain provided by FEC is used to do multiple functions including increasing the maximum span length and/or the number of spans that results in extending system reach, thereby, for increasing the number of DWDM channels in a system which is typically limited by the output power of the amplifiers being used.

This coding gain also decreases the power per channel and increases the number of channels or relaxes the component parameters (e.g. launched power, eye mask, extinction ratio, noise figures, filter isolation) for a given link and lowers the component costs.
Xilinx FEC IP cores are cost competitive and only require a single project licence with no recurring royalty fee.