Vivado Design Suite 2014.1 increases productivity

SAN JOSE, USA: Xilinx Inc. released the Vivado Design Suite 2014.1, the industryÂ’s only SoC-strength development environment.

This release extends the automation of the UltraFast design methodology and delivers an average of 25 percent faster runtimes and 5 percent improvement in performance across all devices. Also new to 2014.1 is hardware acceleration of OpenCL kernels, within Vivado High-Level Synthesis (HLS).

With over 2,500 customers trained on the UltraFast design methodology and 30,000 views of the UltraFast design methodology video tutorial, Xilinx continues to raise awareness and adoption of the methodology developed to increase designer productivity.

By leveraging the UltraFast design methodology recommendations design teams are achieving design closure in weeks versus months spent on similar projects without this methodology.

Now in its second edition, the UltraFast design methodology has been extended to include new best practices for VivadoÂ’s support of 28nm 7 series and 20nm UltraScale devices. The UltraScale architecture applies leading-edge ASIC techniques in a fully programmable architecture to enable multi-hundred gigabit-per-second levels of system performance with smart processing at full line rates, scaling to terabits and teraflops.

The updated methodology also includes high-level synthesis, partial reconfiguration, and verification using the Cadence, Mentor Graphics, and Synopsys flows.