TI launches SoC architecture

LONDON: Texas Instruments Incorporated, headquartered in Dallas, Texas, has launched a system-on-chip (SoC) architecture based on its multi-core DSPs.

The company said in a statement that the architecture consists of a high-speed switch that lets multiple DSPs communicate with and access memory resources.

According to Brian Glinsman, general manager (communications infrastructure business) of Texas Instruments, the architecture supports multiple DSPs operating at up to 1.2-GHz clock frequency and also fixed-point and floating-point processing within each DSP core. At that clock frequency, Brian Glinsman said the statement, the architecture can give, theoretically, up to 256-GMACS and 128-GFLOPS – the result being the highest-performing CPU in the industry.

Texas Instruments also claims that the multi-core SoCs can deliver 5 times the performance of solutions currently available in the market and offer the main processing power for infrastructure products like media gateways, video infrastructure equipment, and wireless base stations.

The company announced that it will introduce a family of products based on the new architecture – beginning with 4-core device for wireless base stations and an 8-core device for networking applications and media gateway.

Texas Instruments explained that a 2-Tbit/s on-chip switch fabric – called TeraNet 2 – offers interconnection between all of the SoC elements.