Techlabs, Aldec launch co-simulation tool

NEW DELHI: The end-to-end solution provider of EDA and power systems planning tools, Techlabs has announced that it has tied up with the US-based Aldec, Inc. to introduce the concept of Co-simulation in India.

Co-simulation, as the name suggests, is a process of simulation of two or more design component in a single environment. In a typical EDA environment, simulation is an important factor during both planning and prototyping stage. Also, at times, one has to work on both proven and unproven logic and integrate the results. Then there is the need to integrate IP cores and legacy designs. All this is very time consuming process.

Not any more. With the launch of the Co-simulation tool first time in India, Techlabs promises to take care of all these issues and much more. The Co-simulation tool not only allows development of System on Chip (SoC) designs in a well-organized manner, it also helps the users expand the functionality of their existing software.

Talking about the concept, Techlabs Managing Director Praveen Kapoor said, "The Co-simulation prototyping board from Techlabs can provide instant confirmation whether or not the design would work properly in a piece of hardware."

Since the prototyping board is controlled directly by the Co-simulation tool and acts as a simulator extension, it does not affect the current design flow or existing synthesizeable HDL code.

The Co-simulation tool accelerates verification of designs containing IP cores and Legacy Designs or verified RTL modules and helps in incrementally adding new HDL blocks. "Besides, the Co-simulation tool would also make the re-use of existing design block a viable option by reducing the verification time and hence improves the time to market," explained Techlabs CEO Sukesh C Naithani.

According to Kapoor, since all design blocks can be instantly swapped between the software simulator and the patented hardware platform, designers would have the freedom to choose between detailed analysis of internal block operations and simulation performance, respectively. As the hardware platform and RTL software simulator are synchronized on an event-by-event basis, the Co-simulation tool provides for ultra-fast design analysis. It is a universal simulator accelerator for HDL simulators that enhances their performance without interfacing with the established design flow,” he said adding that as the platform works seamlessly with these HDL simulators, it is a risk-free option for SoC designers.

"Because the Co-simulation platform provides direct interface to external ASIC devices, designers can test their designs in real applications such as cellular phones, disk drives, industrial controllers and medical test equipment.

Most emulators and hardware accelerators require extensive setups and run only in certified environments. In fact, the tool from Aldec is the only hardware platform that does not require such setups and interfaces directly with simulators with PLI, FLI and other standard interfaces. It also works on any platform, under any OS and with any simulator. It is truly a universal tool for all designers," the company press release claimed.

Talking about the tie-up with Aldec, Inc., Naithani said that Aldec’s aim of eliminating ASIC and SoC design verification bottlenecks through innovative EDA hardware solutions goes very well with Techlabs’ vision of becoming the world-class provider of computer aided engineering tools and services aimed at simplifying clients’ business process.

"The tie-up with Aldec would help Techlabs achieve its goal to innovate and pioneer new design verification solutions, which are complimentary add-ons to the customers existing design environment and EDA tools," he said adding that, "By bringing higher productivity products with a minimal learning curve, we will be in true position to assist the design community in efficient verification and use of silicon technologies."