Synopsys multi-core initiative to accelerate design time-to-results

MOUNTAIN VIEW, USA: Synopsys Inc. announced its multi-core initiative to deploy advanced parallel, threaded and other optimized compute technologies across its Discovery Verification and Galaxy Design platforms, and Design for Manufacturing (DFM) solutions.

The initiative aims to enable IC design companies to easily maximize the throughput of their multi-core compute infrastructure to reduce time-to-results (TTR).

This initiative builds on Synopsys' proven multi-processor and network-distributed electronic design automation (EDA) solutions, including the VCS functional verification solution with native testbench technology for compute farms and the Proteus lithography solution offering near-linear scalability. Additional multi-core-enabled solutions will be delivered throughout 2008.

The combination of increasing IC complexity and shrinking semiconductor features is driving exponential demand for design and manufacturing-related compute resources.

Synopsys' initiative addresses this demand by deploying advanced multi-core software and optimized IT solutions that can deliver breakthrough productivity increases.

The three key components of Synopsys' multi-core initiative to be delivered during 2008 are:

Galaxy Design Platform: The industry's most widely used implementation solution, including Synopsys' Design Compiler RTL synthesis solution; IC Compiler comprehensive place-and-route solution; the PrimeTime suite for sign-off; Star-RCXT parasitic extraction; TetraMAX automatic test pattern generation (ATPG) and Hercules physical verification solutions.

Discovery Verification Platform: Synopsys' comprehensive system-to-silicon verification solution, including System Studio for algorithm design and analysis; VCS functional verification; and HSPICE, NanoSim and HSIM circuit simulation solutions.

DFM Solution: Including the Proteus OPC solution for mask synthesis; CATS mask data preparation; and Sentaurus TCAD tool suite for semiconductor process and device modeling.