Synopsys intros verification compiler to enable 3X productivity

MOUNTAIN VIEW, USA: Synopsys Inc. has announced the availability of Verification Compiler solution, a new product that represents a compelling vision in the industry for system-on-chip (SoC) verification technology and verification roadmaps.

Verification Compiler is a complete portfolio of integrated, next-generation verification technologies that include advanced debug, static and formal verification, simulation, verification IP and coverage closure.

Together these technologies offer a 5X performance improvement and a substantial increase in debug efficiency, enabling SoC design and verification teams to create a complete functional verification flow with a single product.

The combination of next-generation technologies, integrated flows and a unique concurrent verification licensing model enables Verification Compiler to deliver 3X productivity overall - directly addressing the growing SoC time-to-market challenge.

"Altera SoCs are some of the most highly integrated, heterogeneous computing platforms in the industry, combining multi-core ARM processor systems, floating point DSP blocks, high-bandwidth I/O and high-performance programmable logic on a single die," said Ty Garibay, VP of IC engineering at Altera.

"As we migrate our SoCs to a third-generation 64-bit architecture integrated on Intel's 14 nm Tri-Gate process, the design and verification tools we use must operate and communicate seamlessly, giving us the ability to simulate and debug across the RTL, UVM and embedded software domains with a unified compiler and debugging flow. The introduction of Verification Compiler is an important step towards enabling our design teams to significantly improve our productivity."

Advanced technology required for SoC verification
With mobile and the Internet-of-Things driving electronics growth, advanced SoC development faces exponential growth in verification complexity, new power efficiency requirements, increasing software content and tougher time-to-market pressures. Achieving verification closure for these complex SoCs requires a broad set of technologies including advanced debug, static and formal verification, low-power verification, verification IP and coverage closure.

To address this challenging verification landscape, Verification Compiler features a comprehensive set of next-generation technologies, including formal verification, SoC connectivity checking, SoC-scale clock domain crossing (CDC) checking, X-propagation simulation, native low power simulation, and advanced verification planning and management. Verification Compiler also includes the entire portfolio of Synopsys' next-generation verification IP, including the corresponding test suites, all integrated for advanced debug and high-performance simulation.

By integrating these technologies in a single product, Verification Compiler enables SoC design and verification teams to better solve the growing technical and schedule challenges of SoC verification.

"We have been collaborating closely with many of our customers on their most complex verification challenges for many years," said Manoj Gandhi, senior VP and GM, Verification Group at Synopsys. "Over the past few years, we've built a strong portfolio of leading-edge verification software technologies. Verification Compiler takes these technologies to the next level by integrating them into a single product with unmatched performance, capabilities, and productivity, and lays the groundwork for even more advances in the future."