Synopsys intros MinChip technology

CIOL Bureau
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BANGALORE: Synopsys Inc. today introduced the new MinChip technology that analyzes physical design complexity and identifies the smallest routable size for semiconductor designs.


The technology is integrated into the physical design flow in Synopsys’s JupiterXT floorplanning tool and IC compiler place-and-route solution. MinChip technology automates the process of identifying the smallest routable area for a design. Optimal results are achieved in hours, saving weeks of manual effort while taking into account all potential area savings, a Synopsys statement said.

The new die size optimization methodology enabled by MinChip delivers critical value for high-volume applications where even small area savings has a significant impact on overall cost per chip. Die size optimization methodology delivers the smallest possible chip size at tapeout. This new capability automates a task that otherwise requires complex scripts and countless implementation runs to reach the same result. For high volume applications, modest area savings can represent a significant yield improvement.

Antun Domic, senior vice president and general manager, implementation group, Synopsys, said, “Die size optimization enabled by JupiterXT and IC compiler allows designers to incorporate an area-optimization step into their tapeout schedule with minimal effort and the possibility of huge payback because of the reduced area.”

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