Synopsys improves quality of manufacturing tests

MOUNTAIN VIEW, USA: Synopsys Inc. has announced the availability of its TetraMAX small delay defect automatic test pattern generator (ATPG) for use by design organizations worldwide to significantly improve the quality of manufacturing tests.

Customers have validated the new test capability on manufactured designs, identifying problems in some devices that had previously passed standard at-speed tests. Small delay defect ATPG creates patterns to test the smallest defects inside integrated circuits (ICs) that could lead to failures when the devices are operated at full speed.

Targeting these subtle delay-related defects using timing-aware pattern generation can improve the quality of test

compared with existing ATPG technologies. Synopsys will demonstrate the new test feature as part of its power-aware design flow at this year's International Test Conference (ITC) in Santa Clara, Calif., October 23-25.

"Our member companies value innovations that improve the quality of manufacturing tests, and we believe Synopsys' TetraMAX small delay defect ATPG is an excellent achievement," said Yoshio Okamura, vice president and general manager of Development Department-2 at the Semiconductor Technology Academic Research Center (STARC), a research and development consortium founded by major Japanese semiconductor companies.

"Synopsys' new test technology will identify failures caused by small delay defects that were not detectable before. Small delay defect testing has important ramifications for our member companies, and to all semiconductor firms dedicated to continually improving product quality."

Process variations can introduce small delays that adversely affect sensitive paths in a design, leading to circuit failures under certain conditions. Until now, designers could not create tests to reliably detect these small added delays because traditional transition-delay ATPG technologies lacked sufficient timing resolution. Synopsys responded to this challenge by enhancing its pattern generation capability to utilize precise timing information to target very small timing slacks.

Designers can pass a circuit's detailed parasitic information from Synopsys' Star-RCXT extraction tool to Synopsys' PrimeTime static timing analysis tool, then use pin-slack information generated from the timing analysis to create small delay defect patterns using the TetraMAX ATPG technology. The new ATPG technique is consistent with existing design-for-test (DFT) methodologies and does not require changes to a design.

Gal Hasson, senior director of Synthesis and Test Marketing at Synopsys, said: "Synopsys' collaboration with a majority of the world's top semiconductor firms has proven that TetraMAX small delay defect ATPG is capable of identifying subtle timing defects that escape traditional at-speed testing. We regard this successful validation of our timing-aware pattern generation capability as a critical milestone, and anticipate the new TetraMAX feature will lead to lower test escapes and ultimately lower test costs for our customers.