MOUNTAIN VIEW, USA: Synopsys Inc. announced that its 20th EDA Interoperability Developers' Forum will feature keynote speaker Michael Keating, Synopsys Fellow and lead author of the recently released "Low Power Methodology Manual" (LPMM).
"Low power design has become a central issue for the entire industry," said Keating. "Establishing a common methodology for developing low-power chips from the architectural level to delivered silicon can be of enormous value to the entire design community. Many of the basic low power design techniques are rapidly converging so a single, consistent, automation-friendly methodology is possible."
The Synopsys Interoperability Developers' Forum is intended to provide an open environment for EDA tool developers, IC design engineers and IP providers to discuss the industry-critical topic of interoperability. The October 2007 Forum focuses on the latest developments in EDA standards including Unified Power Format (UPF), the Interoperable PCell Libraries (IPL) initiative and the Verification Methodology Manual (VMM).
General Session:
In addition to the keynote presentation, the Forum's General Session showcases the first public presentation on the SOI Industry Consortium, which is focused on promoting the benefits and adoption of silicon-on-insulator (SOI) technology. The event will also feature a low power/UPF checklist based on the open-source Liberty library format and an update on the Liberty Technical Advisory Board.
Morning Session One:
"Interoperability of Analog/Full-Custom Flows" features the latest IPL updates that address broad interoperability issues in analog and full-custom design flows and foundry process design kits (PDKs). Six IPL member companies will demonstrate products interoperating using the proof of concept IPL and OpenAccess Analog Symbol Library in real time.
Morning Session Two:
"Integrating with VMM Methodology for SystemVerilog," focuses on verification. Novas Software presents its Verdi product integration with VMM and how designers have benefited from this methodology. Details about Synopsys' recently announced VMM Catalyst Program which promotes the development and use of EDA tools, verification IP, training and services supporting the VMM verification methodology are discussed as well.
Afternoon Session:
"The Power of One: UPF on the Path to IEEE Ratification," focuses on the Unified Power Format (UPF). UPF is the low power standard for IC design and verification. Following its approval as an Accellera standard, UPF has moved on to the next level of standards credibility as the basis for the IEEE P1801 low power standard. Listen to EDA and IP companies present their support for UPF and P1801, and ask questions about implementation.
"As SoC design and manufacturing become more and more complex, the development and wide-spread support of industry standards becomes a vital link in addressing the needs of IC designers," said Rich Goldman, vice president of Strategic Market Development at Synopsys. "This Forum demonstrates Synopsys' continued commitment to interoperability and we are pleased so many of our competitors are joining us to support open communication in standards development."
The event will take place Thursday, October 25, in Santa Clara, California.