Synopsys’ design solns for new ARM suite of IP

BANGALORE, INDIA: Synopsys, Inc. announced its collaboration with ARM to create an optimized Reference Implementation with Synopsys IC Compiler II for the ARM Cortex-A72 processor.

This will enable engineers to deliver advanced designs for the next-generation of mobile devices.

“We have collaborated with Synopsys to ensure our mutual customers can bring innovative products to market quickly while meeting their performance, power and area targets,” said Noel Hurley, general manager, CPU Group, ARM.

The Reference Implementation for the Cortex-A72 core takes advantage of ARM POP IP in 16nm FinFET Plus process, Synopsys HPC methodology and the latest tools and features in the Galaxy Design Platform. To achieve up to 2.5 GHz performance in a mobile computing power envelope, the Reference Implementation includes support for Synopsys’ Design Compiler Graphical tool for RTL synthesis, IC Compiler and IC Compiler II for place and route, and PrimeTime solution for signoff and physical ECO.

In addition, the Reference Implementation is compatible with the Lynx Design System.

IC Compiler II is Synopsys’ latest offering in place-and-route and is a full-featured, production-ready netlist-to-GDSII implementation system delivering the highest throughput and productivity along with the best quality of results. It offers ultra-high capacity design planning, new clock-building technology and advanced global analytical closure techniques. These technologies enable IC Compiler II to deliver a 5X speed-up in implementation runtime along with half the iterations required to achieve target performance, together providing a 10X boost in throughput.

Building on previous collaborations to enable ARMv8-A based processor and advanced Mali GPU designs as well as the new Reference Implementation for the Cortex-A72 core, Synopsys and ARM are collaborating to extend these solutions across the new IP suite to include: optimized implementation with the Galaxy Design Platform, including IC Compiler II; virtual prototyping with Virtualizer Development Kits (VDKs) for ARM v8-A based cores; optimized simulation, formal verification, advanced debug, verification methodology, as well as the next-generation verification IP, Verification Compiler product and ZeBu solution for emulation; HAPS FPGA-based prototyping systems; and a full chip deisgn environment with the Lynx Design System.

In addition, Synopsys Core Optimization Services have extensive experience helping designers optimize their CPU and GPU cores for performance, power and area.