Synopsys announces multiprotocol DesignWare enterprise 12G PHY IP

By : |January 28, 2014 0

MOUNTAIN VIEW, USA: Synopsys Inc. announced the availability of its multiprotocol DesignWare® Enterprise 12G PHY IP to reduce power consumption and increase performance in a broad range of high-end networking and computing applications.

Architected to address designers’ growing performance/power trade-off challenges, the DesignWare Enterprise 12G PHY enables designers to easily integrate enterprise protocols, including PCI Express 3.0, SATA 6G, 10GBASE-KR, 10GBASE-KX4 (XAUI), 1000BASE-KX, CEI-6G/11G, SGMII, QSGMII, SFF-8431, CPRI, OBSAI and JESD204B, into their system-on-chips (SoCs) with higher performance and up to 20 percent lower power consumption than competing solutions.

The DesignWare Enterprise 12G PHY includes architectural innovations to significantly reduce power consumption for enterprise SoCs. The high-performance analog front-end incorporates power saving features in both active and standby modes of operation. The hybrid transmit drivers support low power voltage mode and high swing current mode, along with other power-reducing features such as L1 sub-states, optional I/O supply under drive and decision feedback equalization (DFE) bypass mode.

                                 

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The high-performance DesignWare Enterprise 12G PHY supports chip-to-chip, backplane and port-side interfaces to enable complex system integration. The flexible Clock Multiplier Unit (CMU) includes multiple PLLs to transmit high-quality data from 1.25 Gbps to 12.5 Gbps across the long and lossy backplanes found in the most demanding applications, including legacy systems.

The analog front-end includes 5-tap DFE, continuous time linear equalization (CTLE) and Feed Forward Equalization (FFE) with advanced algorithms for start-up and mission mode adaptation to enhance signal integrity in high throughput communication channels. The multi-lane architecture with other advanced features like reference clock forwarding and PCI Express aggregation and bifurcation gives designers a flexible, scalable PHY IP solution for high-speed SoCs.

“As a PCI-SIG member for more than a decade, Synopsys has played a valued role in the development of PCIe technology,” said Al Yanes, PCI-SIG chairman and president. “Its support of the PCIe 3.0 architecture helps enable the continued success of the PCI Express ecosystem.”

“With the latest data center and cloud computing trends, such as software defined networking and low power microservers, system architects are increasingly implementing multiple high-bandwidth protocols in a single SoC,” said John Koeter, VP of marketing for IP and systems at Synopsys. “With the addition of the DesignWare Enterprise 12G PHY IP to our broad data center IP portfolio, we can help designers better address performance and power concerns in new cloud computing architectures.”

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