Synopsys announces availability of Discovery verification IP for ARM AMBA 5 CHI standard

MOUNTAIN VIEW, USA: Synopsys Inc. announced the availability of its Discovery Verification IP (VIP) for the ARM AMBA 5 CHI (Coherent Hub Interface) on-chip interface specification.

This standard targets the ARM Cortex-A50 series processors used in high data rate applications common in enterprise markets such as the server and networking markets.

The Synopsys Discovery VIP for AMBA 5 CHI provides an easy-to-use, high-performance verification environment with unique protocol-aware debug capabilities and advanced built-in coverage features designed to accelerate the system-on-chip (SoC) verification closure process.

"Our networking QorIQ SoCs with the revolutionary new Layerscape architecture are designed to enable hundreds Gb/s performance and enhanced packet processing capabilities," said Fares Bagh, VP of Hardware Engineering for Freescale's Digital Networking business.

"Developing the design environment for such SoC complexity required a complete verification framework with a single-testbench and debug methodology from simulation all the way to emulation. As an early collaborator, the deployment of the Synopsys Discovery VIP for ARM AMBA 5 CHI was a critical element to this verification framework as we look to leverage its 100 percent SystemVerilog, UVM-based VIP architecture across all interface and on-chip bus protocols."

"Since its introduction earlier this year, the AMBA 5 CHI protocol has been deployed in several key SoCs to deliver optimal system operation, especially for high-performance applications," said Andy Nightingale, director of System IP, ARM.

"These complex SoCs in turn offer challenging verification requirements. Through our early collaboration, Synopsys' verification IP equips SoC teams with verification, debug and performance analysis technology to accelerate the development of AMBA 5 CHI-based SoCs."

"ARM and Synopsys have a 15-year history of successful R&D collaboration to deliver verification solutions, including SystemVerilog, verification methodology, simulation performance, low power verification, debug, interface IP and, most recently, our verification IP for AMBA 5 CHI interconnect," said Debashis Chowdhury, VP of R&D in the Synopsys Verification Group.

"Through this collaboration, Synopsys continues to deliver advanced verification technology for simulation, emulation, debug and performance analysis to speed the design of advanced ARM-based SoCs."