Sun Microsystems releases design details of MAJC chip

BANGALORE: Sun Microsystems, Inc. has announced the design details of the

MAJC 5200 chip, the first one to use the general-purpose MAJC microprocessor

architecture. According to a company release, the new MAJC 5200 model integrates

two VLIW (very long instruction word) microprocessors on a single piece of

silicon and is designed to handle the real-time flow of multimedia data.

The first MAJC chip design is expected to deliver extraordinary compute and

signal processing performance. "With the design of the MAJC 5200 chip, Sun

is delivering the processing power needed for a new class of convergence

applications," said Bill Joy, founder, chief scientist and corporate

executive officer, Sun Microsystems, Inc., adding, "these new applications

demand an entirely new approach to processing real-time streams of visual and

audio information."

The MAJC 5200 chip is expected to be capable of decoding two MPEG streams in

real time while simultaneously doing a surround sound audio decode or a Web

browsing session, the release added. For example, a user could simultaneously

view two different television programs delivering finance and news while

interacting with a Web site to purchase new business equipment.

In addition, this chip is expected to be able to handle over one hundred

voice-over-IP channels while enabling encryption and decompression of the

packets over a 10 gigabit-per-second Ethernet connection. This means that a very

large number of simultaneous phone conversations could be supported in a

small-footprint gateway server device.

In the area of image processing, the JPEG 2000 test set is anticipated to run

at 78 MB/s while encoding 8-bit sample images. For networked video, two streams

of MPEG-2 data representing five Mbps interlaced sequences have the ability to

be simultaneously decoded, with additional processor capacity still available.

For teleconferencing under the H.263 standard, six decodes and one encode are

expected to be handled in real time. In advanced audio applications, an AC-3

decode of 5.1 channels at 384 kps is predicted to use only seven and one-half

percent of the capacity of one of the 5200's two processors.

The MAJC 5200 chip is expected to have a clock frequency of 500 MHz and is

expected to tape out by the end of this year. Engineering samples are

anticipated in the second quarter of 2000.