SMIC pushes 45nm tech to 40nm, 55nm

LONDON, UK: Aggressively pushing its efforts to keep up with the semiconductor technology pace set by rivals, Semiconductor Manufacturing International Corp is looking more at its 45-nm bulk CMOS to 40-nm and 55-nm activities. The foundry chipmaker’s 45-nm process is based on technology licensed from IBM.

The company has said its 45-nm technology has been implemented at its 300-mm facility in Shanghai and that it has been done ahead of schedule.

The foundry chip manufacturer now looks at doing the same thing at the 45-nm bulk CMOS to 40-nm and 55-nm activities, which in turn would provide the company’s current and new customers with a customized set of solutions to meet their diverse product design-in needs, said EETimes in a report in this regard.

The company, however, has not revealed as to when the additional nodes would become available. It has also stopped short of saying whether the Semiconductor Manufacturing International Corp would implement low-leakage versions of the process to complement a general-purpose process, which the 45-nm node is believed to boast of.

A spokesperson for the company has been quoted as saying that the applications for the additional processes at the at the 45-nm bulk CMOS to 40-nm and 55-nm geometries are much the same as for the original 45-nm process. This means that they include multimedia products, graphics chips, chipsets, and mobile devices such as handsets integrated with 3G/4G.

Meanwhile, Cadence Design Systems, Inc, a provider in electronic design innovation, announced that SMIC has adopted Cadence Litho Physical Analyzer and Cadence Litho Electrical Analyzer to more accurately predict the impact of stress and lithographic variability on the performance of 65- and 45-nanometer semiconductor designs.

The Cadence Litho Electrical Analyzer - the semiconductor industry's first electrical DFM solution in production at leading semiconductor companies from 90 nanometers to 40 nanometers - combined with Cadence Litho Physical Analyzer to create a flow that accurately predicted final silicon results, said a press release.