Silicon Frontline launches F3D, R3D

PARIS: Silicon Frontline Technology, based in Campbell, California, the United States, has launched the latest versions of its products for post-layout verification – the F3D (Fast 3D) for fast 3D extraction, and R3D (Resistive 3D) for 3D extraction and analysis of large resistive structures such as power devices.

In a statement, Silicon Frontline Technology claimed that the latest version of its F3D software demonstrates a performance increase of 10x. Besides, the capacity of F3D and the R3D is unlimited. Designs can be automatically partitioned into blocks of up to 4 million transistors. Each block can be run using one CPU, or multiple CPUs can run a number of design blocks in parallel.

In the earlier version, the block size was limited to a maximum of 1 million transistors, the company said.

Silicon Frontline Technology, founded in 2007, had announced the commercial launch of its first products – the F3D and the R3D – in May 2009. Shortly afterwards, TSMC and UMC, foundries based in Taiwan, said they had validated the F3D for their 40-nm and 65-nm processes.

Aptina Imaging licensed the F3D software of Silicon Frontline to improve its image sensor design accuracy and manufacturing quality.

According to Silicon Frontline Technology, the F3D and the R3D products incorporate patent-pending 3D technology to deliver a ‘Guaranteed Accurate’ solution for full-chip, post-layout verification.