Advertisment

Predictive analysis key for logic designers: Atrenta

author-image
Pradeep
New Update

SAN JOSE, USA: Atrenta invests heavily in the development of its automated SoC design guidance solutions, with over 75 percent of its employees involved in R&D at facilities in San Jose (US), Noida (India), Grenoble (France), Colombo (Sri Lanka) and Shanghai (China).

Advertisment

The company supports its worldwide customer base with direct sales and support offices in Silicon Valley, Southern California, Texas and North Carolina in the USA; France, Germany, UK, Japan, Taiwan, Israel and India and distributors in China and Korea.

Atrenta's SpyGlass Predictive Analyzer gives engineers a powerful guidance dashboard that enables efficient verification and optimization of SoC designs early, before expensive and time-consuming traditional EDA tools are deployed.

Here, Dr. Ajoy Bose, chairman, president and CEO, talks to Pradeep Chakraborty about how Atrenta has been providing early design analysis for logic designers, and how SpyGlass and GenSys platforms are helping the industry. Excerpts:

Advertisment

CIOL: How does Atrenta provide early design analysis for logic designers?

Dr. Ajoy Bose: The key ingredient is something we call predictive analysis. That is, we need to analyze a design at a high level of abstraction and predict what will happen when it undergoes detailed implementation. We have a rich library of algorithms that provide highly accurate "predictions", without the time and cost required to actually send a design through detailed implementation.

CIOL: There is a saying: electronic system level (ESL) is where the future of EDA lies. Why?

Advertisment

AB: This is because the lower level of abstraction (detailed implementation) of the EDA market is undergoing commoditization and consolidation. There are fewer solutions, and less differentiation between them. At the upper levels of abstraction (ESL), this is not the case. There still exists ample opportunity to provide new and innovative solutions.

CIOL: How will this help EDA to move up the embedded software space?

AB: The ability to do true hardware/software co-design is still not a solved problem. Once viable solutions are developed, then EDA will be able to sell to the embedded software engineer. This will be a new market, and new revenue for EDA.

Advertisment

CIOL: How are SpyGlass and GenSys platforms helping the industry? What problems are those solving?

AB: SpyGlass is Atrenta's platform for RTL signoff. It is used by virtually all SoC design teams to ensure the power, performance and cost of their SoC is as good as it can be prior to handoff to detailed implementation. SpyGlass is also used to select and qualify semiconductor IP - a major challenge for all SoC design teams.

GenSys provides a way to easily assemble and modify designs at the RTL level of abstraction. Because a lot of each SoC is re-used design data, the need to modify this data to fit the new design is very prevalent. GenSys provides an easy, correct-by-construction way to get this job done.

Advertisment

CIOL: How does the SpyGlass solve RTL design issues, ensuring high quality RTL with fewer design bugs?

AB: It is the predictive analysis technology. SpyGlass provides accurate and relevant information about what will happen when a design is implemented and tested. By fixing these problems early, at RTL, a much higher quality design is handed off to detailed implementation with fewer bugs and associated schedule challenges.

CIOL: Why is Apple's choice of chips a factor in influencing the global chip industry?

Advertisment

AB: The primary reason is Apple's volume and buying power. Apple is something of a "King Maker" when it comes to who manufactures their chips. Apple is also a thought leader and trend setter, so their decisions affect the decisions of others.

CIOL: How is the global semicon industry doing in H1-2013? Also, do you have any tips to offer?

AB: We see strong growth. Our customers are undertaking many new designs at advanced process technology nodes. We think this speaks well for future growth of the industry.

CIOL: What are the key growth areas and why?

AB: At a macro level, the consumer sector will drive a lot of the growth ahead. For EDA, the higher levels of abstraction is where the growth will be.

semicon