OVP unveils simulation models of Virage ARC

LONDON, UK: The Open Virtual Platforms (OVP) has released free, high-speed simulation models of Virage Logic’s configurable ARC processor cores.

Models of the Virage Logic ARC600 and ARC700 families of processor cores, including the ARC605, have been released. 

Virage Logic and Imperas cooperated on the verification of the functionality of these models. ARC processors are commonly used in audio and video sub-systems and in flash controllers.

The models produced by Virage Logic work with the OVP simulator, OVPsim, where they have shown performance reaching hundreds of millions of instructions per second, a statement from Virage Logic said.

The models, which are free, are available as open source from website of the Open Virtual Platforms (OVP).

The instruction-accurate OVP processor models are and intended to be speedy so that embedded software developers, especially those building hardware-dependent software like firmware and bare metal applications can have a development environment available early to accelerate the software development cycle.

Virtual platforms making use of these OVP processor models can be created or the processor models can be integrated into SystemC/TLM-2.0-based virtual platforms using the TLM-2.0 interface available with all OVP processor models, according to Simon Davidmann, president and CEO of Imperas and founding director of the OVP initiative.