Oticon standardizes on Synopsys’ Design Compiler Graphical

By : |January 4, 2015 0
Reduced congestion and MCMM synthesis cut weeks from schedule
Synopsys

MOUNTAIN VIEW, USA: Synopsys Inc. announced that Oticon Inc., a leading manufacturer of hearing solutions, has deployed Synopsys’ Design Compiler Graphical RTL synthesis solution for implementing all of its hearing solutions ICs.

Minimizing IC area and power consumption while maximizing functionality and performance are key factors in delivering the smallest hearing aids with the best voice quality and feature set.

To achieve these goals, Oticon has widely deployed Design Compiler Graphical’s congestion optimizations and MCMM synthesis technologies and is realizing lower leakage, faster design performance and a highly convergent design flow, shortening schedules by weeks.

“Meeting aggressive power and area budgets within tight schedules is of primary importance for hearing solutions ICs,” said Mogens Isager, lead developer, Physical IC Design at Oticon.

“With Design Compiler Graphical’s advanced congestion and MCMM optimizations, we are seeing 20 percent less congestion in high-density cell areas, improved design frequency, lower leakage power and faster place-and-route runtimes, which enable us to meet all our design goals and save a few weeks of schedule. Design Compiler Graphical is now a standard component of our design flow.”

Design Compiler Graphical addresses challenging design requirements at both established and emerging process nodes. It provides designers with visualization of congested circuit regions and allows them to perform specialized synthesis optimizations to minimize congestion in these areas. Additionally, new optimization technologies monotonically reduce design area and leakage power by an average of 15 percent while maintaining timing quality of results (QoR).

These capabilities in conjunction with MCMM synthesis and shared physical technologies with Synopsys’ IC Compiler place and route solution enable customers to achieve the best timing, area, power and routability QoR, reduce design iterations and deliver their products to market faster.

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