Next-gen FPGA SoC platform for OpenSPARC

CIOL Bureau
Updated On
New Update

SAN JOSE, USA & BEIJING, CHINA: Xilinx Inc. and BEEcube Inc. will unveil a high-performance development environment for multicore UltraSPARC CMT (chip multi-threaded) processors that reduces the time and effort required to design systems using the SPARC architecture.


The companies demonstrated the development system for the first time at the grand opening of an Advanced Research & Teaching Facility for Embedded System Design in Beijing, a joint venture between Beijing University of Technology (BJUT), the Chinese Ministry of Education (MOE) and Xilinx University Program (XUP).

The BEEcube SoC development platform is built upon BEEcube's third-generation, large-scale multi-core processor BEE3 emulator and takes full advantage of the performance and flexibility of Xilinx' flagship Virtex-5 FPGAs.

The platform enables researchers and hardware architects to quickly experiment with large scale, multi-core, multi-threaded FPGA implementations of UltraSPARC CMT processors for a broad set of end-markets including computing, industrial, scientific, medical, aerospace and defense, storage and networking.

Sun Microsystems' UltraSPARC T1 and UltraSPARC T2 microprocessors are the first 64-bit microprocessors available as an open source design.