Nat Semi's new clock jitter cleaners

USA: National Semiconductor Corp. introduced the industry’s first family of clock jitter cleaners capable of providing ultra low-noise clocks without external high-performance voltage-controlled crystal oscillator (VCXO) modules. Using a simple external crystal and cascaded PLLatinum architecture, National’s new clock jitter cleaners provide sub-200 femtosecond (fs) root-mean-square (RMS) jitter to improve system performance and accuracy. This level of performance rivals the most expensive VCXO modules.

The new LMK04000 family consists of five precision clock conditioners: LMK04000B, LMK04001B, LMK04011B, LMK04031B and LMK04033B. These devices feature power-to-noise specifications that place them among National’s PowerWise family of energy-efficient products. The LMK04000B and LMK04001B offer 24.4 mW-ps per channel, while the LMK04031B and LMK04033B are rated at 25.4 mW-ps per channel and the LMK04011B is 37.4 mW-ps per channel.

The LMK04000 devices provide clean clocks to analog-to-digital converters (ADC), digital-to-analog converters (DAC) and other high-performance components used in wireless infrastructure, test and measurement, and medical ultrasound and imaging equipment. Wireless base station applications include single-carrier and multi-carrier GSM (GSM), LTE, UMTS, WiMAX and CDMA networks.

These clock conditioners are well-matched to work with National's high-speed op amps and ADCs, such as the LMH6552 fully differential amplifier, LMH6514/15 digital variable gain amplifiers and ADC14V155 high-bandwidth 14-bit ADC, to provide a complete signal-path system solution.

Precision Clock Conditioners
The new LMK04000 family uses National’s cascaded PLLatinum architecture, which consists of two high-performance cascaded phase-locked loops (PLL), a low-noise crystal oscillator circuit, a high-performance integrated VCO as well as low-noise dividers and drivers. The first PLL can be configured to use a simple external crystal or a VCXO module to provide the jitter cleaning function while the second PLL uses the integrated VCO to perform low-noise clock generation.

These devices feature dual redundant inputs, five differential outputs and an optional default-clock upon power-up. The input block is equipped with loss of signal detection and automatic or manual selection of the reference clock.

Each clock output pair consists of a programmable divider, a phase synchronization circuit, a programmable delay and either a low-voltage differential signaling (LVDS), low-voltage positive-emitter-coupled logic (LVPECL) or low-voltage CMOS (LVCMOS) output driver. The LVPECL and LVDS outputs support clock rates up to 1080 MHz, while the LVCMOS outputs reach up to 250 MHz.

The default-clock is available on CLKout2 and it can be used to provide an initial clock for the field-programmable gate array (FPGA) or the microcontroller that programs the clock jitter cleaner during the system power-up sequence.

National’s LMK04000 precision clock conditioners are supplied in 48-pin LLP packages. National fabricates these products on its proprietary BiCMOS8 process technology in its South Portland, Maine, facility. This state-of-the-art silicon germanium process enables the devices to achieve the lowest jitter and power performance in the industry.