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Mentor Graphics announces verification IP for PCIe 4.0

Mentor Graphics, EDA, EDA tools, semiconductors, verification IP, PCIe 4.0

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Pradeep Chakraborty
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Mentor Graphics
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WILSONVILLE, USA: Mentor Graphics Corp. announced the immediate availability of its new Mentor EZ-VIP PCI Express Verification IP.

The new Verification IP (VIP) reduces testbench assembly time for ASIC (application-specific integrated circuit) and FPGA (field-programmable gate array) design verification by a factor of up to 10X.

Verification IP is intended to help engineers reduce the time spent building testbenches by providing re-usable building blocks for common protocols and architectures. However, even standard protocols and common architectures can be configured and implemented differently from design to design. As a result, traditional VIP components can take days, or even weeks, to prepare for a simulation or emulation testbench.

“When designing with the ARMv8-A architecture and ARM® CoreLink cache coherent interconnects in mobile, networking and server SoCs, our partners have a choice of PCIe root complex solutions,” said Jim Wallace, director, systems and software group, ARM. “ARM has used Mentor’s PCIe VIP library running on Questa and Veloce to help verify critical interactions between PCIe and ARM AMBA interface domains to enable rapid deployment and accurate protocol checking.”

Unlike traditional verification IP, Mentor’s new PCIe EZ-VIP is “design-aware,” eliminating several time-consuming steps in the testbench assembly process. This fast-forwards verification engineers past tedious configuration and implementation set-up tasks, directly to high-value scenario generation, reducing a process that used to take days or weeks to just hours.

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