Magma rolls out chip design tool Talus

BANGALORE: Magma Design Automation Inc., a provider of semiconductor design software, today unveiled Talus, a new integrated circuit (IC) implementation product line that offers automation and virtually unlimited capacity while delivering improved timing, area, power, signal integrity and manufacturability.

The advanced implementation capabilities in Talus are designed to dramatically reduce the design development cycle and design costs, and speed yield ramp-up for ICs targeted at 65-nanometer (nm) and smaller process geometries, the company said in a statement.

“Talus delivers what EDA has long promised,” said Rajeev Madhavan, CEO of Magma. “At each process node, development costs are increasing and profits per design are decreasing. To reverse that trend, IC vendors need true design automation so they can accelerate the design cycle and maximize their engineering resources — that's what Talus delivers.”

The statement further added that Talus provides a complete RTL-to-tape-out platform that concurrently analyzes and optimizes timing, area, power, signal integrity and yield. It enables Automated Chip Creation, a new methodology for IC implementation that drastically improves engineering productivity. With Talus, floorplanning has been transformed into an automated physical synthesis process. Leveraging a new constraint set called Relative Placement Constraints, Talus eliminates the need for the traditionally labor-intensive and time-consuming floorplanning and prototyping tasks.

Design for variability on complex designs is supported through concurrent multi-mode/multi-corner and native on-chip variation (OCV) analysis with timing and crosstalk noise optimizations. Talus' advanced timing capabilities eliminate the need for iterative analysis and optimization runs to meet multiple mode and corner constraints. Talus also incorporates sophisticated routing algorithms developed in conjunction with IBM and the University of Bonn. Talus is the first system in which the entire implementation flow is lithography-aware. This unique capability minimizes the key source of deterministic variability in 65- and 45-nm designs.

Talus' Automated Chip Creation methodology enables designers to create either preliminary or final-quality layouts, physically flat or hierarchically, in just a few hours and for any size design. The process can begin with as little as 10 percent of the design RTL available. With fast and accurate feedback early in the cycle, users can identify the top-level timing constraints that meet block timing budgets, enabling them to avoid timing violations later during chip integration. With each subsequent RTL change, Talus automatically creates multiple floorplans, allowing designers to see in real-time the impact of those changes on chip size.

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