Lattice selects Silicon Frontline for ESD analysis

CAMPBELL, USA: Silicon Frontline Technology Inc. (SFT) an EDA company in the post-layout verification market, announced that Lattice Semiconductor Inc., the provider of innovative FPGA and PLD semiconductor solutions, picked Silicon Frontline's ESRA (ElectroStatic discharge Reliability Analysis) software for fast, full-chip ESD (ElectroStatic Discharge) analysis. ESRA improves the reliability and quality of semiconductors offered by Lattice.

"Lattice is focused on providing customers with the industry's lowest-power, lowest-density, lowest-cost programmable logic devices and full-chip ESD design validation is a critical part of protecting the integrity of our products," stated Choon-Hoe Yeoh, senior director EDA Tools and Methodologies at Lattice. "After extensive evaluations of various options, we selected Silicon Frontline's ESRA software as our standard full-chip ESD sign-off solution for all our FPGA and CPLD designs because it meets our capacity, accuracy, ease-of-use and cost requirements."

"We are proud to have Lattice Semiconductor select our ESD software to verify and improve the quality of their devices," said Yuri Feinberg, SFT CEO. "Because of today's requirements to support multiple power domains, the demands on designers, with respect to ESD analysis, continue to escalate. ESD events are responsible for over 25 percent of silicon failures. Verifying nanometer designs with multiple power domains before silicon test, with our software, can avoid re-designs and re-spins, leading to better quality silicon and satisfied customers."

ESRA provides a full-chip ESD analysis solution. It delivers extraction, simulation, analysis, and debugging capability in one integrated environment. Highlighted resistance and current density violations permit designers to perform layout corrections at any time in the design process.