Junctionless transistors in 20-nm node possible

LONDON, UK: Professor Jean-Pierre Colinge, of Tyndall National Institute, in Cork, Ireland, has said that junctionless transistors could be implemented commercially at about the 20-nm manufacturing node.

Jean-Pierre Colinge is co-author of the paper titled ‘Nanowire transistors without junctions’ that was published in Nature Nanotechnology recently.

The junctionless transistor is based on the use of control gate around a silicon nanowire.

According to Jean-Pierre Colinge, the control gate can be used to modulate the resistance of the nanowire and to ‘squeeze’ the electron channel to nothing – thus turning off the device. Doping is used to produce p-type and n-type FETs, but there are neither steep dopant gradients nor junctions that guarantee simplified manufacturing. 

Such a major change in the structure of the fundamental electronic device, Colinge said, is expected to require a lot of independent research. An introduction at about 20-nm will require companies to switch more or less immediately.

However, a change to the junctionless transistor could fit in with previously forecast moves by the industry away from planar transistors and towards FinFETs and multi- and wrap-around gate structures, Jean-Pierre Colinge said.

According to him, the junctionless transistor is capable of competing now, but it will take time for semiconductor-making companies to get used to the idea, mainly since people are “scared” of the high doping levels.