Imagination reveals key elements of its MIPS CPU roadmap

By : |June 28, 2013 0

LONDON, UK: Imagination Technologies announced new details about its current and future MIPS CPU portfolio.

Imagination has updated its current portfolio of MIPS Aptiv cores, extending each of the Aptiv families with new core configurations. In addition, later this year, Imagination will start rolling out an entire generation of new MIPS CPUs, including 32-bit and 64-bit cores. The new MIPS Series5 generation of CPU cores, codenamed ‘Warrior,’ will incorporate new architectural features and provide best-in-class performance and efficiency for a wide range of applications.

New in MIPS Aptiv

Imagination has extended the award-winning MIPS Aptiv generation of cores, adding a very small-footprint single-core version to the interAptiv family and a floating point version to the microAptiv family. The high-performance proAptiv, multi-threaded interAptiv and compact microAptiv families of cores, are all available in refined, validated configurations offering industry-leading low power and efficiency for today’s designs.

* The proAptiv family comes in configurations from single through to six-core versions with optional hardware floating point

* The interAptiv family includes hardware multi-threading and now comes in single-, dual- and quad-core configurations with optional floating point. The new single-core version of interAptiv removes the extra logic associated with multi-core coherency and L2 cache controller, providing a highly-efficient, multi-threaded single-core processor

* The microAptiv family is available in versions targeting microcontrollers and deeply embedded processors, and now incorporates an optional hardware floating point unit for applications including electric metering and motor control

MIPS roadmap

Imagination will introduce next-generation MIPS ‘Warrior’ cores later this year. Details of the cores are already being shared with key MIPS customers.

The ‘Warrior’ generation of cores will include 32-bit and 64-bit variants with a focus on superior performance efficiency across the high-end, mid-range and entry-level/microcontroller CPUs. These cores are based on the heritage of MIPS, the industry’s most efficient RISC architecture, targeted to deliver the best performance and lowest power consumption in a given silicon area.

Building on the true 32-bit and 64-bit instruction set compatibility of MIPS, ‘Warrior’ cores will provide binary compatibility from the entry-level to the high-end. 64-bit ‘Warrior’ cores have no need for excess ‘baggage’ to execute legacy 32-bit code, and the broad range of tools and applications built for the 64-bit MIPS architecture over the past 20 and more years will seamlessly work with ‘Warrior’ cores.

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