IEDM presentation on SRAM memory cell

MANHASSET: The 55th annual International Electron Devices Meeting (IEDM) of IEEE will be held at the Hilton Baltimore on December 7-9, 2009.

About 215 papers are to be presented by researchers from universities, corporations and government laboratories worldwide at this year’s IEDM.

In two technical papers, researchers will detail the remarkable achievements made in the development of SRAM memory cell.

An SRAM memory cell, made with non-conventional lithography, is claimed to be 43 per cent smaller than the size of the smallest SRAM cell reported previously.

Researchers from the National Nano Device Laboratories, Taiwan, and the University of California, Berkeley, the United States, have built a functional 0.039m2, 6-transistor SRAM cell using a photoresist-free, maskless, nano-injection lithography technique.

The technique of nano-injection lithography uses a gas-phase chemical reaction, which is activated with a finely controlled electron beam, in order to deposit a desired nanometer-scale hard mask pattern for subsequent etching. The reaction can deposit both dielectric materials and conductive masking materials.

According to the researchers from the National Nano Device Laboratories and the University of California, Berkeley, the lithography process – which includes a dynamic supply-voltage regulator and a full TiN gate – is claimed to be a low-cost means to conduct device and circuit verification for 16-nm technology development.

In another paper to be presented at this year’s IEDM, researchers will explain an inter-band tunnelling field effect transistor (TFET). This TFET, built on InGaAs, features on-current of 20uA/um at 0.75V, as well as large on-off current ratio of 104.