IC industry and Dr. Gargini’s lessons

By : |August 1, 2007 0

Those who were fortunate enough to attend the recently held SEMICON WEST in San Francisco had the pleasure of attending a great session on the past, present and future challenges for the IC industry by Dr. Paolo Gargini, Director of Technology Strategy at Intel. I have highlighted the session on CIOL, courtesy, SEMICON WEST.

For those who may not have the time to read this article, here’s a snippet of what Dr. Gargini had to offer. The first lesson, he said, was that, "Something right may still happen even when everything seems to be going wrong.” However, challenges that were continuously posed also needed to be addressed at the earliest, in order to keep moving forward.

Many also predicted several times that some limit would be reached – that chip development would never get below ten nanometers, or below five nanometers. However, the industry was able to produce components with a gate oxide at about 1.2 nanometers.

Later, the game changed to scaling, which led to Gargini’s second lesson – “Predictors of engineering limits have always been proven wrong by the right improvements.” Shrinking silicon technology of the 1990s kept the industry moving forward.

His third lesson was, “It would be wrong to believe that the right fundamental limits don’t exist.” The fourth lesson was, “It is wise to look for the right solutions before things start going wrong.” Dr. Gargini recalled how Intel had announced that 45nm generation was ready. That it included high-k metal gates was only disclosed this January giving Intel the time to work on yields, enhancements, reliability problems, etc.

Gargini quoted Gordon Moore as saying that introduction of high-k metal gates was the single most important innovation in semiconductor manufacturing of the last 40 years!

Interestingly, a few weeks ago, the PULLNANO Consortium announced breakthrough results for 32nm/22nm, which CIOL covered as well. Among other things, the PULLNANO consortium has fabricated a functional SRAM using innovative MOS transistors whose device architecture differs significantly from that of transistors used in 45nm technology node.

These transistors are built using a low power consumption approach based on Fully Depleted Silicon On Insulator (FDSOI), coupled with a gate stack composed of a high-K gate dielectric and a single metal electrode stack. This is said to be the first time that such a compact SRAM cell has been fabricated using FDSOI, high-k dielectric and metal gate together.

Coming back to Dr. Gargini, his fifth lesson was, "It would be wrong to delay taking action and not do the right thing at the right time." According to him, there was a need for re-examining the opportunities for reviewing “old” theories and techniques that didn’t work on silicon.

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