How does logic chip/memory chip work?

Introduction:
Transistor is a solid state, three terminal semiconductor amplifying device. Transistor is the fundamental component of most electronic circuits. Bipolar, and Field Effect Transistor (FET) are two types of transistors. Transistors and other components like capacitors are interconnected to make complex integrated circuits such as microprocessor, logic gate and memory.

FET has gate terminal (to which the input signal is normally applied) and the source, drain terminals (across which the output voltage is developed). Gate terminal is connected to the gate electrode (doped polycrystalline Silicon or metal) while the source and drain terminals are connected to the impurity (Phosphorus, or Boron) doped source and drain regions in the single crystal Silicon substrate. Channel is the region of the semiconductor under the gate electrode separating the source and drain. The channel is usually lightly doped with a dopant type opposite to that of the source and drain.

For example, if the source and drain are doped with Phosphorus, the channel region of the Silicon substrate is doped with Boron. Semiconductor substrate (also known as wafer) is physically separated from the gate electrode by an insulating gate dielectric to ensure that no electric current flows between the gate electrode and the substrate. This configuration of Metal (gate electrode) – Oxide (gate dielectric) – Semiconductor (doped source, drain and substrate) is called MOS transistor. NMOS and PMOS refer to the majority charge carrier in the channel region i.e. for NMOS, the source and drain regions are doped with Phosphorus and electrons are traveling through the channel region. 

During the operation of MOS transistor, an input voltage is applied on the gate electrode. This applied voltage sets up transverse electric field in the channel region. Electric current in the channel is modulated by the electric field. As the induced electric field dictates the current flow, this device is called Field Effect Transistor (FET). Several of these MOS based FETs are interconnected to make logic integrated circuit. Inverter is one such circuit and its functioning is explained in the next section.

NMOS Inverter

NMOS inverter is a logic gate based on the Enhancement – Depletion (E – D) NMOS technology.  Core of this type of inverter consists of two transistors – an enhancement mode MOSFET called the driver and the depletion mode MOSFET called the load. The driver is switched on and off by the input signal. The load transistor connects the power supply voltage (Vdd) and the inverter output.  Gate of the load transistor is electrically connected to the source electrode resulting in zero gate voltage
(Vg = 0). Driver (enhancement) transistor source is connected to the ground while drain is electrically connected to the source of the load transistor and the output.

The threshold voltage of the driver transistor (Vte) is selected between zero and Vdd while the threshold voltage of the depletion mode load transistor Vtd is negative. Input signal to the inverter (Vin) is fed at the gate of the driver transistor, and the output signal is the voltage level
 at the output node Vo.
When there is logic zero input signal (low voltage at Vin) Vg at the driver transistor is less than Vte and hence there is no conducting channel between the source and drain. Since the depletion transistor is ON, the output is electrically connected to Vdd and V0 rises to logic 1.

When the input voltage to the inverter is logic 1 (close to Vdd), the gate voltage (Vg) applied to the driver is greater than Vte . This turns the driver transistor ON. Under this condition, a low impedance path exists between the output node and the ground. Hence, the driver transistor can conduct large current with a small voltage drop across it, allowing the output to go to logic zero. In both these conditions, the logic level at the input is inverted (zero to one or one to zero) at the output of the circuit.

Practical application of the inverter logic gate as an integrated circuit element requires fast switching speed (small propagation delay time), low power dissipation, and small size. These requirements of maximum transistor packing density with minimum power consumption is achieved by designing driver transistor with smallest possible gate area and load transistor having 4x the effective channel length of the driver transistor. Transistors with the desired physical structure, dimensions and electrical properties are fabricated using several Applied Materials equipment such as ion implanter, Silicon and dielectric film etchers and metal, dielectric thin film deposition systems. Manufacturing of NMOS inverter on the single crystal silicon wafer substrate involves total of 30 major processing steps.  These includes implant (5 steps), lithography (6 steps), oxidation (4 steps), deposition (5 steps), etch (9 steps) and diffusion (1 step). Reference 1 provides detailed information on the process sequence used for manufacturing this device.

Memory Chip

Memories store digital data in terms of bits or binary digits (ones and zeros). Separate storage device or circuit element is used to store each bit of data. This storage element is referred to as cell. These elements are arranged in an array consisting of rows and columns. Each cell shares electrical connections with all the other cells in its row and column. The horizontal lines connecting all the cells in the row are called word lines and the vertical lines connecting the columns are called the bit lines. This allows each cell to have a unique address which can be accessed at random through the selection of the appropriate word and bit line. 

In computers, the number of memory bits is usually 100 to 1000 times greater than the number of logic gates. Higher number of bits means memory devices must be as small as possible, must consume very low power during operation and the manufacturing cost of the memory chips should be as low as possible. Figure 3 summarizes the evolution of memory and logic technologies. In its simplest form, semiconductor memories use a combination of transistor and capacitor. In Random Access Memory (RAM), information is stored on cell through charging of the capacitor. Charge on the capacitor needs to be refreshed periodically and this refreshing processes categorizes the random access memory as Dynamic Random Access Memory (DRAM).

Figure 3 Evolution of the memory (DRAM) and logic (microprocessor) chip in terms of number of transistor and cost per bit (Source: IC Knowledge web site)

Dynamic Random Access Memory (DRAM)

Technological developments in DRAM have been focused on low cost, high yield with particular emphasis on low leakage devices and storage capacitor. Each memory cell of the DRAM is made up of a single MOS transistor and a storage capacitor. Gate electrode of the transistor is connected to the word line, the source terminal to the bit line and the drain terminal directly to one of the electrode of the capacitor. Second electrode of the capacitor is connected to a reference potential. Information is stored by charging the capacitor through the transistor and is read out by discharging the capacitor through the transistor.

During the write operation, the word line is energized enabling the transistor to be conducting between the source and the drain. If zero is to be stored, the bit line is not energized and the capacitor is not charged. If a one is to be stored, the bit line is energized and the capacitor is charged to the potential of the bit line signal. During read operation only the word line is energized and a signal is transmitted to the bit line if a one has been stored previously and the capacitor is charged.
Charge stored (Q) in the capacitor is equal to its capacitance (C) times the voltage (V)
 i.e. Q = CV. As the operating voltage (V) decreases the stored charge will also decrease. Higher capacitance is needed for the next generation DRAM operating at lower voltages.

Two major developments in the DRAM technology have been reduction in the capacitor
area without reducing the capacitance value. This is achieved by designing new capacitor shape to fit into a minimum chip surface area and increasing the dielectric constant. Alternative shapes such as trench and stacked capacitors are used along with high dielectric materials such as Tantalum Oxide to meet these requirements.  Reference 5 outlines the recent developments in capacitor design and material integration requirements to develop next generation capacitor.

Applied Materials Silicon etch, and high dielectric constant film deposition  tools are used for this application.

SUMMARY

Logic and memory chip are built using Metal Oxide Semiconductor (MOS) based Field Effect Transistor (FET) and capacitors. Inverter chip uses several transistors connected to result in input signal inverted i.e. zero converted to one at the output. Transistor design parameters such as gate dielectric thickness, channel length and dopant concentration affect the speed, packing density and power consumed by these devices. Memory chip functions by using combination of transistor and capacitor to store and retrieve information.

Design parameters such as capacitor area, dielectric constant and response time are being continuously optimized to allow packing more information on an integrated circuit. Applied Materials’ equipment and processes are used to develop processes and offer integration solutions enabling our customers to manufacture the current and next generation transistors and capacitors.

The author is with Thin Films Group, Applied Materials, India