Good position likely for PLDs in 2009: Altera

HONG KONG & BANGALORE, INDIA: How will the coming year shape up for FPGAs, given the situation where there have been whispers of a possible demand weakness in the FPGA industry?

I discussed this issue, and much more with Jennifer Lo, Senior Marketing Manager, Altera Asia Pacific. Excerpts:

CIOL: How have you been impacted by the downturn?

Jennifer Lo: As you can tell in the newspapers and TV that the economical environment that we are getting into is an extremely challenging one. We also heard news that Gartner has lowered the 2009 semiconductor forecast to “down 16 percent” compared to 2008.

However, comparing to other semiconductor companies, many of which are taking very drastic measures in cutting down cost and preserving capital, Altera is in a very strong position, both financially and product-wise.

Financially, we had taken steps to focus on cost reductions and simplification internally a few years back. We are seeing great results from those earlier efforts. You may check our financial data and find that we are essentially debt-free and have very healthy balance sheet. We continue to be profitable even under the very challenging environment we are in!

Product-wise, we announced a few days ago that we are shipping the industry’s 40nm product. This is a key milestone and we are very excited about it with this new product family, Stratix IV, which offers the industry’s largest density, highest performance, highest system bandwidth and lowest power, targeting customers in a variety of markets, including communications, broadcast, test, medical and military.

Going forward in 2009, we will continue to rollout the rest of the members in the Stratix IV product family. We will continue to execute the new product strategies in the plan with full confidence. However, due to the fact that such has not been publicly announced, I can only share the details with you at a later date.

CIOL: What are you doing about the demand weakness in the FPGA industry?

JL: Lower power, lower cost and smaller space are still the common needs for portable applications for 2009. These needs may drive PLD vendors to focus on architecture and process to address power and cost.  Also, probably work on package to develop a smaller device. Altera's goal is to still focus on these common needs. 

The Altera MAX II Z has offer the lowest dynamic power and comparable static power in industry already. We may focus more on package size on 2009.

CIOL: Although leading-edge FPGAs are scaling to 40-nm and beyond, have the tools caught up with these new and complex processes?

JL: Lowering power consumption and improving customer productivity have been the focus of our product strategies for the past few years. 

Lowering power consumption means lowering costs for customers, not only in the BOM cost (reducing heatsink or cooling requirement), but also the on-going operating cost (fans, air-conditioning costs, etc). At this day and age of ever increasing fuel and electricity costs, this is gaining significance in customers’ selection consideration. Seeing such need, reducing device power consumption has been  a major element in our product planning and  execution.

We mentioned earlier that Altera's Max II Z product in our low-cost CPLD line offers the lowest dynamic power and static power in the industry that is catered for the portable applications. On the high end of the spectrum, with Stratix IV GX, for example, with the advanced 40nm process node, we utilize the “Strained Silicon” technology, lower core voltage of 0.9V, triple gate oxide as well as low-K inter-metal dielectric material low power transceiver designs. In terms of design, we put in extra effort in lowering the overall power consumption in the transceivers as well as optimized DDR memory interfaces.

Coupled with programmable power technology, which allows customers to use high performance (hence high power consumption) circuitry for design along the critical path, while either using low-power circuit on other parts of the design or turning the logic blocks completely off while not in use, all of the process and design innovations work together toward one common goal of lowering the overall power consumption in the customer design.

In customer productivity improvement, we’ve invested in the feature sets in our design software, Quartus II, to enable team-based designs, incremental compilation as well as  faster compilation time compared to other competing software.

We also have a wide suite of IPs in a multitude of applications and technologies, such as our Nios embedded processors, the many memory interfaces and peripherals. Combining all those with our SOPCBuilder tool also enable customers to integrate system designs with very much reduced time and effort. 

CIOL: What is your take on FPGA design starts being quite flat over the last couple of years?

JL: We do see a lot of new market applications for FPGAs apart from the traditional communications market. Out of the many market segments that we participate in, we see that the communications, military and industrial segments will be in better situation than others in the next couple of years, and we will continue to focus in these segments. 

CIOL: How are you tackling complexity, thereby projecting FPGAs as a growth area for 2009?

JL: As mentioned earlier, 2008 has been difficult and Altera expects 2009 to be another very challenging year for the industry. As with other downturns previously, the industry may go through its reformation, which may inevitably involve some weaker companies to either go out of business due to deteriorating business environment or get acquired by stronger companies.

In Altera, based on the strengths we discussed earlier, with both our financial and product positions, we are very confident that programmable logic with its highly flexibility, versatile application will have a good market position in 2009. 

Hardcopy ASIC is our major differentiator from other PLD/FPGA vendors. We are the only company having both an FPGA vehicle to enable fast time-to-market and simultaneously possessing the seamless migration platform to low-cost production support using Hardcopy ASIC.

With the industry trend of fewer and fewer ASIC starts due to the high NRE costs and high justifying volume, there will also be less investment in the ASSP front given the contracting demand. We see Hardcopy as a major competitive edge that Altera has. It will bring us to a different rank in the industry.