Gold Standard unveils 'variability' modeling service

CIOL Bureau
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LONDON, UK: To help chip designers model the performance of circuits made from variable and unreliable nanoscale transistors, Gold Standard Simulations Ltd., a spin-off from the University of Glasgow, has been set up.

Manufacturing-variability and atomic-scale variability are known to be issues as the minimum dimensions of circuits head below 20-nm and creating design rules for the worst case is no longer appropriate, said an EE Times report. Attempting to avoid variability means that the number of design rules rises exponentially and guard-bands effectively put a stop to miniaturization. Also, circuit performance and yield can be affected by variations in structure can resulting in variable and unreliable performance.


The outcome is that designers need to take statistical variability into account when designing circuits. Supporting this is one of the main goals of the Gold Standard Simulations (GSS).

The company was created by Professor Asen, who is currently company CEO. He holds the James Watt Chair in Electrical Engineering at the College of Science and Technology at Glasgow University.

The company, which is based at the university, will also offer courses in statistical variability on how to design variability-resistant and reliable devices and circuits. It is also subcontracted to provide simulation services for the MODERN (MOdeling and DEsign of Reliable, process variation-aware Nanoelectronic devices, circuits and systems) project — a €26 million (about $33 million) European collaborative research project looking at how to design computer chips