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Follow UsBANGALORE: In recent years, communications equipment vendors as well as consumer electronics system developers have had to deal with an exponential increase in the amount of data that their systems have had to process and transmit.
System designers are now discovering that traditional tried and true methods of transmitting data within their systems is no longer viable for the data rates that their systems have to service. Often bandwidth requirements in these systems can exceed several gigabits per second.
For quite some time, system designers employed large numbers of links comprised of single-ended signaling technologies such as Transistor-Transistor Logic (TTL) and LVTTL (Low Voltage TTL). At the time, TTL technologies provided an easy and cost-effective solution for shuttling the data within the application.
As the data rate requirements within the systems increased over time, designers simply increased the number of signaling lanes in order to attain the data throughput needed for their application. This parallel scaling of channels approach provided designers with only a temporary solution to their data transport needs.
As system size, cost and power efficiency started to become critical design requirements, system designers started to employee differential signaling technologies such as Emitter-Coupled Logic (ECL) / Positive Emitter-Coupled Logic (PECL) and Low Voltage Differential Signaling (LVDS).
These differential-signaling technologies enabled designers to increase each data channel's frequency while maintaining signal integrity and keeping their power budgets in check. Differentials signaling technologies were able to breathe new life into parallel data buses. However, as data rates continued to climb at an ever increasing rate, even the parallel differential signaling technology approach was unable to keep up with the bandwidth requirements of modern communication and consumer applications.
Today, system designers have to increase the data throughput within their systems as well as contend with smaller form factor requirements, improved power efficiency (especially for portable applications), failsafe and quality of service requirements.
Given the increasing requirements set on system data links, many designers are turning to Serializer/De-Serializer (SerDes) technology as an attractive replacement for the parallel signaling technologies they have used in the past. By using SerDes technology, data link designers can address key issues that tend to plague modern high-speed data link design.
These key concerns are:
- Signal integrity
- Power and heat dissipation (thermal performance)
- Board space usage
- Redundancy and fail safe implementation
To better understand the impact that SerDes technology can have on modern high-speed data link design, let's examine how SerDes addresses each of the key concern areas noted above.
Signal integrity
The preservation of signal integrity is one of the key elements in the design of data links for almost any system. This is especially true as data rates begin to scale beyond one gigabit per second. In most cases, signal integrity issues result in data corruption, which can lead to poor system performance or an outright failure of the application function.
In parallel data link implementations, impairments such as jitter, signal attenuation, and channel-to-channel skew are just a few issues that can lead to signal integrity problems for parallel data links.
In the case of jitter, single-ended signaling technologies are more susceptible to noise as there is no common mode noise rejection capability typically exhibited in differential signaling schemes.
Various noise sources often show up as jitter in systems resulting in data bit errors. This is especially true as data rates move past one gigabit per second. At the higher data rates, timing margins become much tighter as the unit interval (the time to account for one data bit) shrinks.
While parallel approaches using differential signaling technologies overcome some of the signal integrity issues found in single-ended implementations, they are vulnerable to issues such as channel-to-channel skew caused by mis-matches between parallel data lines. This mis-match can result in data bits arriving at the destination point at non-deterministic times, which can result in data bit errors as well as system timing errors.
Also, most parallel signaling approaches, regardless of whether single-ended or differential signaling is used, typically does not encode the data being transmitted. Encoding can be used to provide DC balance as well as transition density. In cases where no encoding scheme is used, the data on individual data links can become susceptible to data patterns that exhibit a long run of ones or zeros (data run length issue). Often run length issues result in missed data bits.
By using SerDes technology, system designers can reduce the impact of many of the signal integrity issues that have been identified. Gigabit SerDes lemploy LVTTL parallel interfaces for easy interfacing to existing parallel data sources, as well as high-speed differential serial I/O using technologies such Current Mode Logic (CML) or Voltage Mode Logic (VML).
In most cases, SerDes devices have built-in data encoding and decoding functionality. These encoding mechanisms often employ industry standard algorithms such as 8b/10b coding or variants such as 4b/5b. A coding scheme such as 8b/10b helps ensure that the serial data stream is DC balanced and, therefore, less susceptible to run length issues that were discussed earlier.
Additionally, SerDes embeds clocking into the serialized data output stream as well as perform clock data recovery on the serial receive data. In this way, clock information is carried with the data rather than clock information being carried on a separate data line as is the case with parallel data link approaches.
As described above, using SerDes devices to implement data links within today's electronics systems, helps minimize signal integrity issues that tend to be associated with single-ended and differential parallel high-speed signaling approaches.
Power and heat dissipation
Modern electronic system designs are becoming feature-rich in terms of their implementation, as well as becoming smaller in size and more power efficient. In fact, form factor and battery life are key application parameters for many types of electronic systems today.
Shrinking system size is highly correlated with heat dissipation as well. Good power management design and heat management tends to be a holistic systems-level effort, typically considered part of the system partitioning effort.
One place where systems designers have been able to make great strides in lowering their overall power requirements is at the data interface level. Specifically, system designers have been able to replace single-ended or differential parallel data buses, within their systems, with SerDes-based data links. This approach has drastically reduced system power requirements while enabling system designs to scale to higher data rates.
For example, designers of data buses within communication systems equipment have successfully leveraged SerDes technology to increase systems port density while keeping power and thermal budgets in check. Consider the power needed to move 10 Gigabits of data over a backplane (See Figure 1).
The traditional parallel approach needs to employ ~16 lanes of LVDS signaling technology for each direction, so full duplex environments need to employ ~32 LVDS lanes (running at ~622 Mbps). Assuming typical LVDS buffer power numbers, the overall power needed just for the data signals is ~2 watts.
In addition to power consumption, the amount of board space used is very large in comparison to the SerDes-based approach. The SerDes approach utilizes 10GbE XAUI SerDes technology that provides four full duplex links running at 3.125 Gbps with embedded clocking.
Typically, modern XAUI SerDes devices provide power dissipation numbers in the 1 Watt range. This amounts to a 50 percent power savings compared to the parallel LVDS approach. In systems where multiple 10 Gbps links need to be supported, the advantage of using SerDes becomes even more evident.
Using SerDes technology has enabled communication systems designers to greatly increase system port counts while keeping system power and heat dissipation issues in check, as well as reducing system form factors to meet market demands.
Figure 1. Ten-Gigabit Backplane with 32 lines of differential LVDS data
Board space usage and system foot print
For many of today's electronic devices, form factor is a critical component of the overall design objective. A key component in achieving the target form factors for system designers is the circuit board design. In particular, it's the usage of board space by the ICs that comprise the electrical design of the system.
In recent years, system designers have been able to reduce board space usage by moving system data link design from historically being parallel implementations to serial implementations using SerDes technology. One example is using SerDes in today's handheld devices such as cell phones and portable entertainment devices.
Today's portable entertainment and communication devices require the movement of high-resolution graphics and video data from the central videoprocessing unit to an LCD-based display. Using the conventional parallel data link design approach requires the circuit designer to allocate space for large parallel connectors, as well as routing space on the circuit board for the signals (See Figure 3).
In contrast, a SerDes-based serial link design approach requires a much smaller serial connector and drastically smaller routing space to be allocated for the data signals. In the example shown, using TI's mobile Flatlink 3G SerDes SN65LVDS301/302 enables the designer to save considerable circuit board space in addition to power savings that he would enjoy.
Flatlink 3G SerDes helps reduce parallel buses from up to 27 bits to just three differential lanes of sub-LVDS signals. This savings can directly impact the types of form factors that are achievable for today's portable entertainment and communications devices.
Figure 3. Flatlink 3G SerDes and Parallel Signaling Implementations.
Redundancy and failsafe implementation
Today's communications and mission critical computing systems need to provide end customers with a high degree of reliability. In many cases, a systems outage can cost end customers millions of dollars of revenue, reduced customer satisfaction ratings and, in some cases, result in safety hazards.
For these reasons, communication and enterprise computing system designers have made system reliability a key component of their overall system design goal.
Systems reliability should be approached holistically permeating every aspect of a system's design. Areas that are especially vulnerable are data links between key components of a system. These data links can take the form of backplane trace, point-to-point cable connections, and point-to-multi point data links over copper trace. These are just a few examples of the type of data links used within communication systems.
Often designers identify critical data paths within their systems that need redundant paths in case the main data path stops functioning. These failsafe paths allow designers to pre-program systems firmware to switch over to redundant paths in case the primary path stops functioning.
If designers used a parallel signaling approach to implement their primary data path, then creating a redundant backup link needs the same number of data links. In the case where a 2.5 Gbps link is implemented using 32 lanes (full duplex) of LVTT signaling, another 32 signaling lanes needs to be implemented for the redundant link in addition to clocking and control signals that may be needed. However, if the data link was implemented using a SerDes approach, then adding a redundant link is simplified to adding another Serdes that only consumes two more differential signaling lanes (for full duplex operation).
If a system contains multiple critical high-speed data links that need to be replicated, then the impact of using SerDes-based data links versus parallel data links is substantial. The SerDes approach has the potential to save systems designers board space, keep power requirements manageable, as well as help designers work within the confines of the thermal envelope for their system.
Using serial link approach for many types of communication system data links often is the best choice when it comes to implementing fail safe and redundancy. Using SerDes-based data links for the high data throughput links within a system can be a critical component in a designer's overall strategy for managing and implementing the reliability requirements of their system.
Conclusion
Examples provided show that using SerDes-based serial links to implement critical high-speed system data buses can have a dramatic impact on the overall design of a system, as well as its performance. As systems from portable hand held devices to large networking equipment evolve, they will need to support more data throughput, be more power efficient, have increased reliability and, in most cases, support smaller form factors.
All of these macro system requirements are key reasons that today's systems designer should consider using SerDes-based data links within their designs as a key component for solving data link issues that they are likely to face.
About the author
Atul Patel is the marketing and new business development manager for Gigabit SerDes products within the high-speed interface products group at Texas Instruments.