Advertisment

Fujitsu Kansai-Chubu Net-Tech shortens design time by 40 percent

Cadence Design Systems, C-to-Silicon Compiler, Kansai-Chubu Net-Tech, EDA, EDA tools, EDA industry, semiconductors

author-image
Pradeep Chakraborty
New Update
Cadence
Advertisment

SAN JOSE, USA: Cadence Design Systems Inc. announced that Fujitsu Kansai-Chubu Net-Tech Ltd (KCN) utilized the Cadence C-to-Silicon Compiler to shorten turnaround time by 40 percent compared to its traditional RTL process for a complex 100G transport system design.

KCN used the SystemC-based design approach for the transport system pipelines, reducing code size by more than half, and used the C-to-Silicon Compiler high-level synthesis for quick iterations to tune the functional specification and generate the optimized RTL implementation.

By changing the design constraints to the C-to-Silicon Compiler, KCN was able to explore different micro-architectures and significantly reduced the place-and-route turnaround time. Fixing a place-and-route issue with traditional RTL design at Fujitsu took three days, but only half a day with the C-to-Silicon Compiler.

“Our highly integrated 100Gbps transport systems operate at very high frequency, which presented a major design challenge,” said Masao Nakano, design engineer, Device Development Department, Network Products Division, Fujitsu Kansai-Chubu Net-Tech. “By designing at a higher level of abstraction in SystemC, our design team was able to implement the customized hardware much more quickly and effectively."

semicon