Flexras showcases automatic hybrid RTL/gate partitioning at DVCON 2014

PARIS, FRANCE: Flexras Technologies, the provider of high performance partitioning design suite tools for FPGA-based prototyping, will demonstrate Wasga Compiler and showcase its user-friendly hybrid RTL/Gate partitioning approach for predictable FPGA-based prototyping at the Design and Verification Conference (DVCon 2014), on March 5, 2014.

Zied Marrakchi, Flexras CTO, will present a tutorial entitled "The best of both worlds: Timing driven hybrid RTL/Gate partitioning for predictable FPGA based prototyping" at booth #904.

Traditional prototyping solutions manage DUT partitioning either in RTL or in gate level and fail to propose predictable and efficient flow allowing to quickly bring-up FPGA based SoC prototype.

This tutorial shows FPGA-based prototyping challenges and presents an innovative methodology unifying the benefits of both gate-level partitioning and RTL partitioning, providing error free implementation and predictable short time-to-prototype.