Fastest-running 8051 MCU IP core available from CAST

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Harmeet
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WOODCLIFF LAKE, USA: An 8051-compatible microcontroller core with 26.85 times the performance per MHz of the original 8051 chip is now available from semiconductor intellectual property provider CAST, Inc.

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Modern 8051 implementations like this new S8051XC3 Super-Fast 8051 MCU Core offer energy, area, and easy development advantages that make them smart choices for offloading application processors in complex systems; managing analog sensors or radios in Internet of Things and wearable electronics devices; or running deeply embedded systems. The benefits of the S8051XC3 now available from CAST are especially competitive:

- A Dhrystone 2.1 performance rating of 0.252 DMIPS/MHz yields an unmatched 26.85 times speed up over the original 80C51 chip operating at the same frequency.

- Maximum CPU frequency exceeds 500 MHz for a class-leading effective increase of more than 1,000 times over 80C51 chips (40nm G process).

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- Real-world performance is boosted thanks to an ultra-fast interrupt response-as low as three cycles-without the need for additional silicon- and power-consuming interrupt controllers.

- Silicon area usage starts at a low 6.2K gates (65nm LP) for the CPU, and remains highly competitive through all options and configurations.

- Dynamic power consumption as low as 2.4μW/MHz rivals that of low-power 32-bit processors and is lower than other 8051s. Efficiency further benefits from energy-saving Dynamic Frequency Scaling, low-power mode support, and the ability to process more while running at a lower-than-maximum clock frequency.

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- Inexpensive single-wire hardware debug pods, 100% compatibility with standard 80C51 code, and support by Keil and other popular debug environments facilitate smooth development.

- Cost-effective licensing with no royalties helps satisfy the most demanding economic requirements.

The S8051XC3 achieves these competitive advantages by incorporating processor innovations rarely applied to 8-bit microcontrollers, including branch prediction, multiple instructions issued in one clock cycle, single-cycle multiplication and division, and even a separate, Harvard-like, data-bus.

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