Energy efficient SoC designs: a new paradigm

BANGALORE, INDIA: Designers today continue to be challenged with the need to manage power, timing and signal integrity concurrently throughout the design flow and must evolve to enable design for energy efficiency.

Alok Mehrotra, managing director, Magma Design Automation talks to Divya Girish of CIOL about the importance of energy efficient SoC designs in the industry and the new techniques that designers can use to reduce power in today’s ICS.

CIOL: The SoCs today contain both analog and digital elements. For more effective and cost-effective IC implementation, designers need a mixed-signal SoC design environment? Can you comment on this?

Alok Mehrotra: This is very true that SoCs have become the prevalent integrated circuits addressing the compute, communication, consumer and mobile applications. The SoCs contain both digital and analog content and analog design is becoming critically important to semiconductor companies as increasingly product differentiation resides in the analog functions. For efficient and cost-effective SoC implementation, it is imperative to have a good mixed-signal design environment. But analog design flows have changed little for decades.

Analog design is often a critical bottleneck in the chip design process with design corner exploration requiring massive iterations in simulation to converge. Design of analog derivatives requires extensive redesign, with little analog reuse and migration of analog designs to new processes takes prohibitive time and resources. The layout effects at small geometries forces much iteration between circuit design and layout.

The Titan Accelerators of Magma deliver huge value to semiconductor companies by augmenting their analog flows to improve analog design productivity and enable analog design reuse. The Titan Mixed-Signal Design Platform is the first full-chip mixed-signal design environment. Titan tightly integrates analog implementation and verification while delivering first-time-correct, predictable mixed-signal designs. Unlike other design solutions, Titan also integrates digital implementation providing a quantum leap in efficiency for mixed-signal chip development.

CIOL: Can you elaborate on the importance of energy efficient SoC designs in the industry and the new techniques that designers could use to reduce power in today’s IC?

AM: Designers today continue to be challenged with the need to reduce power for their SoCs targeted to mobile applications. Traditional power optimization techniques are effective but insufficient to achieve the targeted energy efficiency.

New techniques achieve dynamic power reduction through activity driven clock gating and physically aware optimization. The Chill product of Magma performs activity driven combinatorial and sequential clock gate optimization. This power-aware netlist optimization results in dynamic power reduction of up to 20 per cent on power optimized designs.

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CIOL: How do you look at the Indian market and what are the trends that you see in the market today?

AM: Large and complex digital designs have been implemented in India on the most advanced process nodes. There is also significant expertise in India for analog/mixed-signal IP design as many semiconductor companies have their library (cell, I/O, memory, Analog IP) design teams based in India. As product differentiation increasingly resides in the analog functions, there is a rise in cutting edge SoC designs in India leveraging the analog expertise.

CIOL: Alok, you have taken over as Magma Design Automation' Managing Director from Vivek Raghavan. What are your plans and initiatives this year?

AM: Magma has an indomitable spirit and has come out of the downturn with multiple new products like Tekton, Titan, FineSim and Chill, to name a few. These provide a magnitude of productivity benefit just like the unified data model and flow did to digital implementation and was adopted by the competition. Magma has a significant lead providing 5-20X speedup and we plan to proliferate these benefits to the customers. There is also emphasis on advanced development to further our lead.

CIOL: Have you planned for any acquisitions or tie ups with any firms this quarter?

AM: There is widespread evaluation and deployment of these solutions of Magma. We are tying up with local firms to provide required models/views and services. Stay tuned for press announcements.

CIOL: Can you explain more about Titan Analog Layout Accelerator (ALX) and Titan Analog Virtual Prototype (AVP)?

AM: The Titan environment includes the comprehensive Titan Mixed-Signal Design Platform, and a set of breakthrough point-tool technologies known as the Titan Accelerators.

The Titan Mixed-Signal Platform, mixed-signal design platform that integrates implements and verifies while delivering first-time-correct, predictable mixed-signal designs.

Titan Accelerators are advanced technology solutions that dramatically improve analog/mixed-signal design productivity and reuse. Essentially, with Titan accelerators, we are bringing digital design style flow to analog/mixed signal world. The Titan Accelerators can be used separately as point tools to augment existing tool flows, or combined to create a comprehensive high-performance analog/mixed-signal design solution.

Titan Analog Layout Accelerator (ALX)

Titan Analog Layout Accelerator (ALX), an integral part of Magma's Titan Mixed-Signal Design Platform, solves today’s analog/mixed-signal custom layout design migration and re-targeting challenges. Titan ALX automates analog layout migration to new technologies. The migrated layouts are usually DRC clean and preserve the analog layout intent carefully expressed in the previous layout. Titan ALX improves reuse of existing high-quality circuit layouts and minimizes the number of design rule check (DRC) and design for manufacturing (DFM) errors that must be fixed by the IC mask designer. This results in significant reductions in the amount of time, effort and costs of custom layout design. It also shortens time and effort required to implement layout changes in sensitive analog circuits.

It also handles the most complex DRC and DFM rules by leveraging a novel and proprietary layout model that supports layout abstraction, hierarchy, PCells and also extracts and meets most analog constraints, eliminating time-consuming manual entry.

Titan Analog Virtual Prototyper (AVP)

Titan Analog Virtual Prototyper (AVP) creates fast and accurate prototypes of the layout of analog blocks and captures layout-dependent proximity effects early in the circuit design phase, allowing designers to avoid time-consuming schematic-to-layout iterations. The same layout- dependent effects can be used in traditional simulation frameworks to ensure layout-aware simulation. Titan AVP delivers a simple user interface that provides early visibility into parasitic R and C, as well as proximity effects including shallow trench isolation (STI) stress, well proximity effect (WPE), oxide definition to oxide definition (OD-OD) spacing and, poly-to-poly spacing. Titan AVP also includes a detailed device placement engine that produces a high-quality, DRC-clean layout.

It creates fast and accurate device-level prototypes, accelerates layout-to-schematic convergence, improves layout designer productivity and delivers best quality of results with minimal manual intervention.