Design start activity CAGR to increase 4.8 percent from 2013-2018

PHOENIX, USA: Today, silicon designs show rapidly increasing levels of complexity in response to end user demands for more connectivity and the ability to use that connectivity in applications like downloading video, video conferencing, device hot spots, increasing camera resolution for richer photos and better screen resolution to enhance user experience.

An additional trend is to include sensors of every type for a better interface and interaction with the outside world. All these features come at a cost which is increased device complexity. New Semico Research, ASIC Design Starts: Growth Continues as Markets Strengthen, states that despite device complexity, design start activity CAGR will increase 4.8 percent from 2013-2018.

"The drive towards offering increased connectivity options to end users in many market segments, and the need to corresponding increase the computational resources in support of the more robust connectivity options, is pushing device complexity levels to new heights," said Rich Wawrzyniak, senior market analyst, Semico Research.

"The increase in device complexity also has a great impact on the third party IP market and ultimately on ASIC design costs as designers strive to meet rising market expectations and requirements. This in turn pushes the need for new silicon solutions and the rise in ASIC Design Starts is a reflection of this"

New research findings include:

* Advanced Performance Multicore SoCs gate count is increasing at a CAGR of 19.5 percent from 2013-2018.

* Value Multicore SoC's CAGR will be 22.2 percent.

* 1st time SoC design efforts are also increasing in 2014 at a 5.2 percent rate.

* Basic SoC design starts CAGR will grow 16.4 percent.

* Overall CAGR for average complexity levels is 19.4% for all ASIC types measured in the study.