CEVA intros vector floating-point DSP core

MESA, USA: Addressing the wireless infrastructure modem chip market, rather than the handset chip market, CEVA has introduced the CEVA XC4500 DSP core, which they claim to be "the world's first vector floating-point DSP specifically designed for advanced wireless infrastructure solutions."

The new core incorporates a range of features squarely aimed at infrastructure applications, including a baseband-dedicated instruction set architecture (ISA), IEEE-compliant floating point support on full vector elements delivering up to 40 GFLOPs performance, comprehensive multi-core support, a fully cached architecture and hardware managed coherency.

Unlike wireless handsets, where asymmetric processing systems are pre-configured and optimized for specific use-cases (often employing more than one type of DSP core), wireless infrastructure typically employs Symmetric Multiprocessing (SMP) through many similar cores, which the XC4500 directly accommodates.

Of course, hardware accelerators (for turbocoding, etc.) are supported by CEVA's Tightly Coupled Extensions (TCE). It is also noted that CEVA has collaborated closely with ARM to ensure comprehensive support for their latest industry-standard interconnect and coherency protocols, enabling their mutual customers to leverage the inherent advantages of designing ARM + CEVA-XC multi-core SoCs.

CEVA asserts that the new architecture enables customers to address any wireless infrastructure use case, including baseband for small cells (Pico, Metro) to macro base stations and cloud RAN (C-RAN), Wi-Fi offloading, wireless backhaul, and remote radio heads. CEVA has already licensed the XC4500 to an un-named Tier-1 vendor, so we'll have to guess who for now.