CebaTech launches CebaRip cores library

CIOL Bureau
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EATONTOWN, USA: CebaTech Inc, an innovative intellectual property (IP) provider, has announced the launch of its library of rapidly tunable silicon IP cores, CebaRIP cores, targeted at system-on-chip (SoC), ASIC and FPGA designs.


The first four members of the CebaRIP library implement leading standard data encryption and compression algorithms used extensively in storage, SAN, NAS, and network applications. CebaRIP cores can be tuned for reuse in multiple application scenarios, each with different application-specific performance, power, area and cost requirements. Moreover, multiple disparate cores can be configured in a plug-and-play ensemble to boost performance and provide a system level solution.

"After licensing CebaTech’s tunable GZIP compression IP core, we determined the need for three new features which required significant design changes. CebaTech executed the changes and delivered the new, verified RTL in four to five days," commented Jiebing Wang, VP of Engineering, Hifn, a provider of storage and network security products. "CebaTech’s rapidly tunable IP approach delivered a core that exactly met our requirements, and in a market-beating cycle time."

CebaRIP cores leverage CebaTech’s high level synthesis (HLS) flow, based upon its C2R Compiler solution, to meet customer-specific application requirements significantly faster and more cost-effectively than traditional IP development flows. In addition to standard CebaRIP cores, CebaTech also develops rapidly tunable cores that implement customers’ proprietary algorithms.


“Data management IP cores such as compression, encryption, deduplication and so on, are the natural first step in our CebaRIP core roadmap,” commented Ramana Jampala, CEO, CebaTech. “In our extensive engagements with storage and network equipment designers, these data management algorithms are an ongoing target for new and modified implementations at both the chip and subsystem level.”

CebaRIO core library

The first four cores in the library consist of a data encryption core, two data compression cores, and a data decompression core. All cores use a stream interface or a PCI interface.

Data encryption core: The CebaRIP AES data encryption core implements the Advanced Encryption Standard algorithm, and is compliant with the IEEE Standard P1619 for the cryptographic protection of data on block-oriented storage devices. It can be configured to support 128-bit, 192-bit and 256-bit cryptographic keys, and can be customized to deliver only AES encryption or only AES decryption. With a 100 MHz clock, data throughput ranges from 1 Gbps to 25 Gbps, depending upon area constraints.


Data compression cores: The first compression core, the CebaRIP GNU zip (GZIP) core, complies with the RFC1951 and RFC1952 standards. It offers optional dynamic Huffman tables for maximum compression, and a configurable hash table width to optimize memory area. The GZIP core achieves compression ratios in excess of 2. With a 100MHz clock, data throughput ranges from 500Mbps to 5Gbps, depending upon area constraints. The second compression core, the CebaRIP Lempel-Ziv Ross Williams (LZRW3) core, implements the Ross Williams lossless data compression algorithm, with compression ratios in excess of 2, and data throughput of 2Gbps, or higher.

Data decompression core: The CebaRIP GUNZIP core decompresses data previously compressed by any GZIP-compliant algorithm, and is compliant with the RFC1951 and RFC1952 standards. It supports stored mode, and both static and dynamic Huffman trees, and achieves a data throughput in the range 500Mbps to 5Gbps with a 100MHz clock, depending upon area constraints.

“Our flexible delivery model enables the customer to choose the most effective path to an on-time, on-specification product,” commented Chad Spackman, CTO, CebaTech. “We can deliver the CebaRIP cores stand-alone for chip integration by the customer; or we can integrate them into a turnkey chip design. Moreover, we can deliver a turnkey, CebaRIP-enabled, board-level coprocessor subsystem that boosts in-system algorithm execution performance by an order of magnitude or more.” CebaTech delivers all CebaRIP cores as synthesizable Verilog RTL source code, accompanied by a simulation environment and scripts, and a comprehensive user’s guide.

All four CebaRIP cores are available now.