Cadence's Encounter to take on Synopsys' Galaxy?

BANGALORE, INDIA: Some time in December 2008,  Cadence Design Systems launched the Cadence Encounter Digital Implementation System, a configurable digital implementation platform delivering incredible scalability with complete support for parallel processing across the design flow.

In an interaction with Rahul Deokar, Product Marketing Director, Cadence, we attempt to find out more about Encounter and whether it takes on Synopsys' Galaxy Custom Designer. Excerpts:

CIOL: What exactly can the Encounter Digital Implementation System do? And, why now? Will this take on Synopsys?

Rahul Deokar: The new “Encounter Digital Implementation System” is a next generation high-performance, high-capacity RTL-GDSII design closure solution with the industry's first End-to-End Parallel Processing flow that enables all steps of the design flow to be multi-CPU enabled: from floorplanning, placement, routing, extraction to timing and signal integrity signoff.

At its core is a new memory management architecture and end to end multi-CPU backplane that provides scalability with increased performance and capacity to reduce design time and time-to-market.

Yes, it surpasses the other solutions available in the marketplace based on the following capabilities and features:

* Ultra-scalable RTL-to-GDSII system with superior design closure and signoff analysis for low-power, mixed-signal, advanced node designs.
* End-to-end multi-core infrastructure and advanced memory architecture for unparalleled scalability of capacity, design turnaround time, and throughput.
* Robust design exploration and automated floorplan synthesis and ranking solution.
* Embedded signoff-qualified variation analysis and optimization across design flow.
* Integrated diagnostic tools for rapid global timing, clock and power analysis/debug.

Here’s a list of benefits that it provides designers:

* Significantly reduces design time, schedule and development risk
* Increased productivity through automation; superior quality of results
* Configurable and extensible platform that ensures maximum utilization and ROI; upgrades proven design flow and amplifies existing expertise.
* Interoperability across package, logic, custom IC design, and manufacturability

CIOL: According to Cadence, it provides complete support for parallel processing across the design flow. Does this mean that designers can fully harness the power of multicore computing?

RD: Yes, the End-to-End Parallel Processing Flow is supported across the entire design flow and consequently, designers can fully harness the power of multicore computing. Today's designers commonly have Dual CPU or even Quad CPU machines on their desktop. The Encounter Digital Implementation System allows designers to leverage their multi-CPU hardware and gain significant TAT improvements on the design cycle time and overall development schedule.

The new Encounter end-to-end Multi-CPU backplane delivers Ultra-Scale Performance gains up to 16X in key areas like routing and timing closure. All steps of the design flow are multi-CPU enabled: from floorplanning, placement, routing, extraction to timing and signal integrity signoff. For instance, on a production design,  when the Encounter Digital Implementation System is run on four CPUs, you can get a 3.2X performance boost across the entire, end-to-end design flow. 

CIOL: Designers are said to be reporting dramatically improved design time, design closure, and faster time-to-market for advanced digital and mixed-signal devices. By what factors, and against which other tool(s) has this been rated?

RD: Cadence's Encounter Digital Implementation System has been developed working in close collaboration with over 15 customer partners who have extensively used, validated and now, deployed it. Customers are already seeing overall design cycles significantly shorted by 25-30 percent, which translates to multiple weeks or even months. These significant improvements are against competitive tool flows in their current methodology.

CIOL: What exactly is meant by “Encounter offering new technologies for silicon virtual prototyping, die-size exploration and RTL and physical synthesis, providing improved predictability and optimization in early stages of the design flow"?

RD: Large scale design complexities (Increased functionality, Predictability, Productivity) pose one of the biggest challenges. Designs are getting huge at 100M + gates, 100+ Macros in the design, putting significant requirements on design tools, particularly, floorplanning of these macros and the whole design becomes a huge challenge.

The new Silicon Virtual Prototyping capabilities of Automated Floorplan Synthesis and Die Size Exploration help out exactly on that front. These can quickly provide floorplanning for that large 100M + gates, 100+ Macro design. And not just one floorplan, but designers can provide multiple criteria (say along the lines of timing or power or area or congestion) and you will get multiple floorplans with their rankings; and all this in a matter of minutes.

Essentially, you could finish your breakfast or lunch (depending upon how fast you eat!) and be back to have multiple floorplans that you can then pick and choose from...and then proceed to implementation.

CIOL: Obviously, targeted at 45nm/40nm/32nm, etc., how can/does it anticipate and address majority of the new problems associated with these geometries across the entire flow?

RD: The main customers include semiconductor companies working on leading-edge 45- and 32-nanometer designs, with aggressive design specifications including 100 million or more instances, 1,000-plus macros, operating speeds exceeding 1GHz, ultra-low power budgets, and large amounts of mixed-signal content. 

The challenges facing these designs comprise of an increasing demand for design tool performance/capacity and design features for challenging ultra-large scale designs in the areas of low power, mixed signal, advanced node and signoff analysis. In addition, small market windows and product life-cycles and the cost pressures further exacerbate the situation.

The Encounter Digital Implementation System’s core design closure capabilities plus the new advanced node technologies, including litho-, CMP-, thermal, and statistical-aware optimization provide comprehensive manufacturing-aware and variation-aware implementation, and an end-to-end multi-core infrastructure for fast, predictable design closure even on the most challenging designs.

CIOL: What kind of work has gone into reducing the memory footprint of the most memory-retentive applications?

RD: At the core of the new Encounter System is an innovative memory architecture that enables capacity and performance Gains of 30-40 percent for full flat and hierarchical designs, even if you are running on a single-CPU machine. The R&D team has developed an advanced memory defragmentation algorithm that allows the applications to be extremely memory-frugal …and that memory-efficiency enables designers to handle their biggest 100M+ instance designs.

CIOL: There are parallels with Synopsys' Custom Designer for AMS. How true? Also, there seem (there will) to be every chance of Virtuoso and Encounter coming together. Pl. comment.

RD: Synopsys’ Custom Designer for AMS is their entry into the full-custom/analog design marketplace, where the Cadence Virtuoso platform is a strong incumbent.

The biggest challenge for mixed signal designers today is the efforts/resources involved in taking design data from the full-custom/analog tools to the Digital Implementation tools...and back and forth…in never-ending iterations.

Now, with the new Encounter Digital Implementation System, designers get the seamless full-custom/analog and digital design implementation interoperability…with unified constraints handling, mixed-signal floorplanning and ECO. It executes off a common design database (OpenAccess), enabling edits made in one design environment (e.g. Virtuoso) to be easily seen in the other design environment (e.g. Encounter).

It also enables the design team to easily transfer the design data, to determine the optimal floorplan based on analog and digital constraints. For example, the analog design team moves pins on the analog block, when the design is opened in Encounter, the modified pin locations are easily seen and the digital design team can execute a pin optimization to re-align the pins at the top-level.

In addition, the user can enter routing constraints in either Encounter or Virtuoso, and implement mixed signal routing in either environment. Top-level routing constraints could be defined within Virtuoso, then the top-level routing completed using the mixed signal routing functionality within Encounter.

And customers are already seeing their overall design schedules significantly reduced.

CIOL: Elaborate on the DFM practices embedded throughout the end-to-end parallel processing flow.

RD: At 45nm, random and systematic process variability is a significant cause of yield loss, lower performance and higher power consumption. Manufacturing effects (Lithography, CMP, etch, and statistical process variations) need to accounted for. These impact not only the printability and design rules but also induce electrical variability. You could have 20-30 percent difference in timing in your design or 300 percent variation in leakage power in your design.

The new Encounter Digital Implementation drives design yield and performance higher with a comprehensive manufacturability-aware solution that encompasses systematic (lithography, CMP, thermal) and statistical timing and leakage power analysis as well as optimization…leveraging the end-to-end parallel processing flow.

The new Encounter system handles all the regular requirements like 32nm design rule support, via reduction and via-doubling, and the physical impact of manufacturing. The key difference is that the manufacturing effects are not an after-thought but Encounter takes a prevention, analysis and repair approach within digital Implementation.

For instance, the embedded Litho-hotspot prevention capability can address majority of the potential Litho violations very early in the design flow. Also, Encounter uniquely accounts and optimizes for the manufacturing impact on timing, SI and power.