Cadence to unveil IO-SSO analysis suite at EPEPS conference

SAN JOSE, USA: Cadence Design Systems Inc. will give the first public demonstrations of its new IO-SSO Analysis Suite at the EPEPS conference Oct. 27 to Oct. 30 in San Jose.

EPEPS (Electrical Performance of Electronic Packaging and Systems) is the premier international conference on advanced and emerging issues in electrical modeling, analysis and design of electronic interconnections, packages and systems.

The Cadence IO-SSO Analysis Suite is a single-vendor solution that provides accurate system-level simultaneous switching noise (SSN) analysis, addressing coupled signal, power and ground networks across chips, packages and printed circuit boards (PCB). It delivers an unparalleled combination of accuracy, speed and ease of use.

The IO-SSO (input/output simultaneous switching outputs) Analysis Suite complements Cadence implementation tools and provides a complete solution for multi-fabric extraction, system-level connectivity and high-speed DDR interface simulation that includes the effects of SSN. Cadence is unique in its ability to deliver implementation, extraction and simulation across chip, package and PCB.

In addition to the new product, visitors to the Cadence table 5 can learn more about the latest advances coming from the integration between Allegro and Sigrity technology for both signal and power integrity.