Cadence, Mentor standardize on Open SystemVerilog

SAN JOSE & WILSONVILLE, USA: Cadence Design Systems Inc. and Mentor Graphics Corp. announced they will standardize on a verification methodology based on the IEEE Std. 1800-2005 SystemVerilog standard. The Open Verification Methodology (OVM) will deliver a tool-independent solution for designers and verification engineers that promotes data portability and interoperability.

It delivers on the promise of SystemVerilog with established interoperability mechanisms for verification IP (VIP), transaction-level and RTL models, and full integration with other languages commonly used in production flows. The OVM will include a robust class library and be available in source code format.

Cadence and Mentor have contributed both technology and resources to develop the foundation of the methodology and the libraries. The methodology will be made available under a standard open-source license, Apache License, Version 2.0.

Accelerating SystemVerilog adoption
"The OVM solves one of the biggest issues facing SystemVerilog adoption today," said Robert Hum, vice president and general manager of Mentor Graphics Design, Verification and Test Business Unit. "Customers seek confidence that their investments in verification will be re-usable in the future. Having a methodology that works on a number of widely installed simulators and verification tools provides the confidence to move to SystemVerilog."

The OVM and supporting class library include the foundation-level utilities necessary for building advanced object-oriented, coverage-driven verification environments, and reusable VIP in SystemVerilog. The OVM reduces the complexity of adopting SystemVerilog by embedding verification practices into its methodology and library. The OVM will significantly shorten the time it takes to create verification environments, easily integrate verification IP and ensure code portability and re-use.

Moshe Gavrielov, executive vice president and general manager, Cadence Verification Division, added: "With the OVM, Cadence and Mentor are delivering an efficient SystemVerilog-based tool-independent solution to help solve our combined customers' key design challenges. The industry as a whole will benefit with a much higher degree of interoperability, verification IP development and reuse, and ease of integration."

Unlike some alternatives, the OVM library will be open source, SystemVerilog IEEE-1800 compliant, and portable to any simulator supporting that IEEE standard. Under the terms of the Apache 2.0 license, it will also be easy for users and IP developers to re-ship the OVM code or derivatives and get support from multiple EDA vendors.

The OVM supports a unique mix of RTL and transaction-level abstractions for SystemVerilog and other high-level languages that support system-level design and verification. The next generation of system-on-chip (SoC) design is already increasing customer demand in the area of transaction-level modeling and verification. This growing demand will include the need to combine software-based simulation, hardware-based verification platforms, and established transaction-level interface standards.

A preliminary release of the OVM is slated for availability for selected customers in Q3-2007. A production release that includes methodology and supporting library is scheduled to be available in Q4-2007. Additional functionality is planned for 2008. Cadence and Mentor have collaborated to ensure that the OVM will run on their simulators, and enable backwards compatibility with their existing environments, AVM from Mentor Graphics, and Incisive Plan-to-Closure Methodology (URM module) from Cadence.