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Cadence, IBM team up for IP cores in SoC designs

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CIOL Bureau
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LONDON, UK: EDA vendor Cadence Design Systems Inc. and IBM team up to create intellectual property cores for usage in SoC designs.

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In the agreement, companies would build up double data rate memory PHY cores, memory controllers, and protocols for example, PCIe and Ethernet for use on 32-nanometer silicon-on-insulator manufacturing processes. The technology would be utilized in servers, video games and other devices.

"Qualifying and integrating composite IP is an expensive and growing burden for a lot of our clients," Vishal Kapoor, vice president of product management at Cadence, has been quoted as saying by EETimes.

He added that the company looks forward to teaming up with IBM to ease some of these troubles for engineering teams as they struggle with SoCs and systems that would only keep on growing in size and complication.

According to a related report that quoted Marie Angelopoulos, a director with IBM Microelectronics, the IP IBM is functioning on with Cadence would offer state-of-the-art building blocks that will let the tech major’s clients build more authoritative, higher bandwidth networking and communications technology.

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