Cadence enhances Virtuoso platform

BANGALORE-Cadence Design Systems, Inc. today announced that it has optimized its Virtuoso Custom Design platform. With the availability of a new chip integration flow, coupled with the newest release of its Virtuoso Chip Editor. By using these solutions together, designers will, for the first time, be able to perform full-scale physical integration across multiple design domains, including analog, custom digital, RF, memories/arrays, and digital standard cells from a full custom point of view.

This new generation Cadence technology offers up to more than 10 times performance improvement over existing custom design solutions. It is also capable of shortening physical design integration from one month to approximately two weeks in a typical advanced mixed-signal design with over 1.5 million transistors.

Cadence's chip integration flow and Virtuoso Chip Editor provide designers an automated physical design integration solution from floor-planning through chip finishing and tape-out, resulting in significant productivity gains and faster time-to-market. Building upon Cadence's commitment to drive open collaboration for its customers, the new chip integration solution provides a seamless bi-directional integration path to and from the Cadence Encounterä Digital IC design platform through the OpenAccess database.






"The industry needs flows and tools which address the lack of interoperability that hinders the speed at which complex SoCs have to be produced," said Steve Schulz, President and CEO of the Silicon Integration Initiative (Si2). "The fact that the new Cadence Chip Integration flow and Virtuoso Chip Editor are based on OpenAccess offers designers greater flexibility and faster SoC assembly across multiple design environments."

The Cadence Virtuoso platform is integrated with the Cadence Encounter platform through OpenAccess, ensuring interoperability between custom and digital design environments. This versatility enables the right solution to be applied to the right design task. The chip Integration flow also builds upon the OpenAccess database, allowing the full custom designer a clear, seamless integration path into the digital design environment

In addition, Cadence is releasing an enhanced version of its Virtuoso Chip Editor - Version 3.3- To further increase layout productivity. Highlights of version 3.3 include immediate visual feedback on design rule violations and advanced connectivity awareness That speeds up chip finishing by alerting the user of accidental opens and shorts. Virtuoso Chip Editor 3.3 offers more efficient editing of full-chip finishing tasks. Supported by robust design tools and a "meet-in-the-middle" methodology that combines the speed of top-down design with the silicon accuracy of bottom-up design, Cadence's new chip integration flow embodies the critical elements required to successfully develop mixed-signal custom designs. This includes the capability to bi-directionally pass data between multiple design domains, floor-planning capability to facilitate top-down and bottom-up design early on, analog routing capability to facilitate continuous evolution, early and frequent parasitic and analysis capability, and chip finishing capability for large design databases.






CIOL Bureau