Cadence announces Allegro TimingVision environment

SAN JOSE, USA: Cadence Design Systems Inc. announced new Allegro TimingVision™ environment, which speeds up timing closure by up to 67 percent.

Available within Cadence Allegro PCB Designer, the TimingVision environment makes it possible for PCB designers to save significant time in ensuring that signals in an interface meet timing requirements. This is an increasingly important capability as data rates increase and supply voltages decrease in today's advanced protocols, including DDR3/DDR4, PCI Express, and SATA.

TimingVision environment uses an embedded timing engine to analyze the entire interface structure and develop timing goals to help designers visualize real-time delay and phase information directly on a canvas. This greatly reduces manual editing, overall implementation time and designer effort.

When combined with the Cadence Sigrity™ power-aware SI analysis tool, TimingVision environment enables rapid implementation and tuning in compliance with standard interfaces, diminishing trials and errors in fixing timing issues.

TimingVision environment is ideal for any PCBs that include advanced high-speed interfaces and is especially suited to PC, tablet, smartphone and cloud data center infrastructure applications.