C-to-Silicon Compiler can take EDA to next level

SAN JOSE, USA & BANGALORE, INDIA: Cadence Design Systems Inc. recently announced the C-to-Silicon Compiler, which is said to be the next-generation of HLS (high-level synthesis) technology. It eliminates historical barriers to HLS adoption and delivers the quality of results and net productivity gains that engineers need.

The C-to-Silicon Compiler produces RTL (register transfer level) with quality at or above the 90th percentile of manual RTL design, while increasing engineering productivity up to 10X. HLS reduces manual effort required to produce RTL, and enables designers to avoid syntax errors common in traditional methodologies.

First  up, what will this product actually do for the EDA industry? According to Steve Svoboda, marketing director for system level design products, Cadence Design Systems, this product can actually take EDA to a new level in terms of delivering additional productivity to designers.

"When design compiler and logic synthesis came, it was during the golden era of the semiconductor industry. Productivity was increasing rapidly. But the problem is, since the early 1990s, there has been no real change in the RTL design methodology. The only productivity increase has come out in form of design re-use," he says.

"This (C-2-Silicon Compiler) could re-energize semiconductor and EDA industries by at least 10X times. About 20 years ago, there was 10X productivity increase. By having HLS, we can now close the gap and tackle the chips more effectively now," he contends.

Manual RTL coding not efficient
In IC design, the RTL is a way of describing the operation of a digital circuit. In RTL design, a circuit's behavior is defined in terms of the flow of signals (or transfer of data) between hardware registers, and the logical operations performed on those signals.

RTL abstraction is used in hardware description languages (HDLs) like Verilog and VHDL to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived. Currently, verification engineers have to write RTL code manually using Verilog or VHDL languages. This method has been the norm for over 15 years now. While it was revolutionary when first introduced, with the current complexity of chips, this type of manual RTL coding is not efficient. It can lead to mistakes and is time consuming!

The hard reality is that (until now) HLS (high-level synthesis) tools have been unable to deliver the quality of results (QoR) and expected net productivity gains to justify broad adoption. For the most part, RTL developers work much the same way today, as they did in the early 1990's, except that today's IC designs are 50x to 100x larger and more complex.

C, C++ and SystemC are languages that are more flexible and easier to use for coding algorithms and doing any kind of architecture exploration than Verilog or VHDL. Currently, designers use C and SystemC for architectural exploration, but finally implementing the algorithm manually in Verilog/VHDL languages. In effect, they are designing twice, once in C, and then in Verilog for the RTL. Clearly, this is inefficient, time consuming and can lead to errors. That's where Cadence's C-to-Silicon Compiler comes in!

High-level synthesis (HLS) tool
Svoboda, Cadence's marketing director for system level design products, says that the C-to-Silicon Compiler is a high-level synthesis tool.

"This is an area that has been tried for a long time. Some other companies are also trying products in this area. The key question is: Why is Cadence doing it now? This has been an acute problem. Basically, the key challenge in HLS is: how do you find the optimum schedule for hardware resources? When you want to execute some algorithm, and then later, execute it in hardware, you want to take the advantage of parallelism, and find the optimum schedule."

According to him, the difficulty in finding the optimum scheduling is the timing estimate. In order to generate these very high accuracy timing schedules, the nominal timing estimates are out of context. You could get differences in fan-in and fan-out. "These dramatically affect impedances, etc. Basically, you are not getting the physical information into the timing estimate," Svoboda adds.

He notes: "This tool can accurately predict the timing estimates. Logic synthesis ability is embedded into the tool. We are embedding Cadence logic synthesis inside the HLS. The HLS transforms C, and C++ into RTL."

"Therefore, we created a solution that goes directly from C to gates. A designer can use any logic synthesis tools he/she wants. We have embedded the RTL compiler from Cadence, so that we can get much better timing and much better results."

Physical synthesis has also been taken care of. "The concept is to try to bring whole context of design to physical level, so you can generate extremely accurate timing," adds Svoboda.

Can it now assumed that the RTL will be free of syntax errors? Svoboda says: "We have embedded logic synthesis inside our HLS tool. This is an industry first, so far. The RTL is correct by construction. The tool generates RTL as per a strict set of rules. And, there are no semantic errors either."

Handling verification
And what about the verification part? How does the C-2-Silicon Compiler handle verification? "We've two ways of handling this," says Svoboda. "We call it a timing approximate model. The internals of the blocks are not shown, but the timing of the block is. These are equivalent to the functioning of the RTL. The second way is by generating scripts that work with the Calypto tool, a formal verification tool." The Calypto verifies that the RTL code generated by the C-to-Silicon Compiler is functionally equivalent to the original SystemC code.

Will the C-2-Silicon Compiler compete with custom design projects? As per Svoboda, the C-to-Silicon Compiler does not compete with custom design projects. "Custom design projects typically utilize transistor-level design. The C-to-Silicon is made to work within a standard ASIC design-flow," he says.

How does it accelerate or improve verification? The C-to-Silicon Compiler both improves and accelerates verification. The timing-approximate fast hardware models (FHMs) run 80-90 percent the speed of untimed C-models (or two-three orders of magnitude faster than RTL). This enables hardware-software co-verification with greater timing accuracy.

Does it allow room for people to use third-party synthesis tools, along with the proprietary Cadence synthesis tool? Says Svoboda: "The C-to-Silicon Compiler outputs IEEE-standard Verilog RTL. Therefore, the output can go to any third-party synthesis tool. However, as the RTL output is generated using timing estimates from Cadence RTL Compiler, designers will get the best quality of results when using RTL Compiler for logic synthesis."

Predicting power and performance
Another key issue with designers is to better predict the performance and power. How does the Cadence tool handle these? Because of embedded logic synthesis, C-to-Silicon Compiler can predict performance and (in principle) power better than other high-level synthesis tools.

Svoboda adds: "The power estimation/optimization are key feature sets planned for the upcoming releases of C-to-Silicon Compiler. We believe those capabilities will enable designers to create designs that are much better optimized for power, since design decisions with greatest power impact are made at the system-level."

Handling hardware allocation and scheduling
Next, how does the C-to-Silicon compiler handle hardware allocation and scheduling operations? The C-to-Silicon Compiler handles hardware allocation and scheduling using various proprietary algorithms and heuristics. Many of these are based on previous research at Cadence Berkeley Labs.

"However one should note that the better quality of results/performance of C-to-Silicon is due primarily to its inherent ability to generate more accurate timing-estimates than other HLS tools. The higher accuracy timing estimates result from the embedding of logic synthesis within the HLS tool/process, which enables the gathering of full-context gate-level information to derive the timing estimates. Other HLS approaches rely on pre-characterization of technology libraries, which is not accurate enough, because those gate level estimates are only nominal values, and do not take into account the full-context of the design (fan-in, fan-out, buffers, etc.)," notes Svoboda.

What about ESL tools?
So what happens to ESL (electronic system-level) tools? Do those disappear? He believes that this tool will help the ESL market.

Svoboda concludes: "We now have a methodology to do design creation in C++ and SystemC. For example, they do virtual prototyping, hardware-software co-design, etc. In the past, when engineers created designs, they had to re-design in C++, etc. Our tool creates the RTL automatically for them. So, this could re-energize the ESL market very well."