Altera reveals details of Stratix V FPGA family

SAN FRANSICO: Programmable logic dealer Altera Corp has unveiled details regarding its 28-nm high-end Stratix V FPGA family, by saying the devices would present up to 1.6 terabits per second (Tbps) of serial switching capability, 1.1 million logic elements and 53 megabits of embedded memory. It also stated that family would in addition offer up to 3,680 18x18 multipliers and integrated transceivers operating up to 28 gigabits per second (Gbps).

Altera also stated that it would make use of the high-performance manufacturing procedure from foundry Taiwan Semiconductor Manufacturing Co. (TMSC), a clear difference from superior competitor Xilinx Inc. In the month of February, Xilinx said it would change to TSMC for manufacturing at the 28-nm node. However Xilinx, which is placing particular importance on low power consumption at the 28-nm node, selected TSMC's high performance/low-power manufacturing procedure.

As per Luanne Schirrmeister, senior director of product marketing at Altera, the key is at all times striking a balance between both the performance as well as power consumption.

According to Altera, TSMC's high-performance process, that utilizes high-k metal gate technology, can offer approximately 35 percent higher performance than different process options and 30 percent lower total power compared with earlier generations.

Xilinx' February announcement compared to the standard high-performance procedure, the high-performance/ low-power procedure delivers FPGAs that are about 50 percent lower in static power. This contributes to a 50 percent decrease in total power compared to earlier generation devices, as per Xilinx. The company's development tools will in addition reduce dynamic power to the extent that 20 percent through pioneering clock management, according to Xilinx.

Altera said its 28-nm Stratix V family shall consist of four variants: Stratix V GT, featuring integrated 28-Gbps transceivers targeting 100G systems and more; Stratix V GX, which features 600-Mbps to 12.5-Gbps transceivers; Stratix V GS, optimized for high-performance digital signal processing (DSP) applications with 600-Mbps to 12.5-Gbps transceivers; and Stratix V E, suited for ASIC prototyping, emulation or high-performance computing applications.

Stratix V devices shall in addition feature tweaks to Altera's adaptive logic module (ALM) architecture, adding to 800,000 extra registers in the biggest device to take full advantage of logic competence, Altera said.