Altera intros first 40nm FPGAs, HardCopy ASICs

SAN JOSE, USA: Enabling designers to achieve new levels of integration and innovation, Altera Corp. announced the industry’s first 40-nm FPGAs and HardCopy ASICs. The Stratix IV FPGAs and HardCopy IV ASICs, both with transceivers options, provide unprecedented densities, performance and low-power leadership.

The Stratix IV family has up to 680K logic elements (LEs), 2X bigger than Altera’s Stratix III family, currently the largest FPGAs on the market. The HardCopy IV ASIC family offers equivalent densities as the Stratix IV devices and features up to 13.3 million gates. Altera 40-nm devices meet the diverse high-end application needs in a large number of markets such as wireless and wireline communications, military, broadcast and ASIC prototyping.

With the increasing demand for services such as video over Internet, high-speed wireless data and digital TV, designers need to deliver solutions that provide higher data rates, higher interface bandwidths, and increased data processing all in a power-efficient manner. To address these design challenges, Altera is leveraging its innovations in transceivers, memory interfaces, low-power technology and FPGA core architecture to offer new capabilities with its 40-nm devices.

Manufactured on TSMC’s 40-nm process, the Stratix IV FPGA family is comprised of two variants, an enhanced variant rich with memory and digital signal processing (DSP) resources (Stratix IV E FPGAs) and an enhanced variant with transceivers (Stratix IV GX FPGAs).

Stratix IV GX FPGAs offer up to 48 transceivers operating at up to 8.5Gbps, which provides designers with the industry’s highest available bandwidth, more than twice the bandwidth of any other FPGA. Stratix IV GX FPGAs also feature hard intellectual property (IP) support for PCI Express (PCIe) Gen 1 and 2 and also supports a wide range of protocols including, Serial RapidIO, XAUI (including DDR XAUI), CPRI (including 6G CPRI), CEI 6G, Interlaken and Ethernet.

To address the low-power demands of customers, the Stratix IV family members feature Altera’s patented Programmable Power Technology. This power-saving technology optimizes logic, DSP and memory blocks to maximize performance where needed while delivering the lowest power elsewhere in the design.

For the first time, Altera offers a transceiver-based ASIC option with the new HardCopy IV ASIC family. Using the Stratix FPGAs in design delivers the benefits of FPGA hardware and software co-design and co-verification—saving months in time to market—and the use of HardCopy ASICs delivers the benefits of ASICs in production.

“Today’s announcement significantly widens the density, performance and low-power advantages of the Stratix series versus competing offerings,” said John Daane, president, CEO and chairman of Altera. “Combined with the HardCopy ASIC family, Altera is the only company that can offer a complete high-performance solution that allows designers to quickly move from concept to volume production.”

The company also announced enhancements to its Quartus II design software and delivered IP solutions optimized for 40-nm products. Quartus II software v.8.0 enables designers to achieve efficient team design and fast time to market through the highest performance, logic utilization and lowest compile times in the industry.

Customers can start their Stratix IV designs using Altera’s Quartus II design software v.8.0. Engineering samples of the first member of the Stratix IV device family will be available in the fourth quarter of 2008. Customer tapeouts for HardCopy IV ASICs will start in the third quarter of 2009.