Altera highlights FPGA-acceleration technology for software programmers

SAN JOSE. USA: Altera Corp. demonstrated its FPGA-based acceleration technologies to system designers and software programmers at SuperComputing 2014 (SC14).

Altera’s participation at SC14 includes several demonstrations that show how FPGA accelerators are being used to increase performance, lower power consumption and lower latency in high-performance computing, networking and storage applications. FPGA-accelerated systems can deliver a significant performance-per-Watt advantage over standard CPU- and GPU-based servers.

Altera showcased in its booth various FPGA acceleration technologies and programmer-friendly tools including the industry’s first FPGAs capable of up to 1.5 TFLOPS of throughput and the industry’s only OpenCL-conformant solution for FPGAs. SC14 is being held in New Orleans, Louisiana from November 17-20.

Altera’s in-booth demonstrations included:

* TFLOP Floating Point Performance on an FPGA: Altera offers the world’s first IEEE 754-compliant FPGAs capable of delivering up to 1.5 TFLOPS floating-point performance. This demonstration shows how Altera FPGAs can meet the requirements of computationally intensive applications, such as HPC, radar, scientific and medical imaging, by showing a 20 nm Arria 10 FPGA-based development kit running matrix multiply at a full TFLOP.

* Coherent Shared Memory between a CPU and FPGA: This demonstration will feature Nallatech’s OpenPOWER CAPI Developer Kit with coherent shared memory between an IBM POWER8 CPU and an FPGA accelerator leveraging IBM’s Coherent Accelerator Processor Interface (CAPI). CAPI enables system architects using IBM POWER8 CPUs to significantly improve system-level performance by using the FPGA as a hardware accelerator.

High-performance, Low-latency 25G/50G Ethernet IP: This demonstration shows developers how FPGAs and best-in-class IP from Altera can lower latency and increase performance in next-generation data centers. The demonstration features Altera’s 25G and 50G Ethernet IP over QSFP28 direct attach copper cable with multiple 25-Gbps serial lanes.

* Pedestrian Detection and Motion Estimation: These two demonstrations use a low-cost development board to show how quickly and easily algorithms can be implemented and accelerated in an FPGA. The demonstrations were developed using OpenCL and run on a low-power, low-cost Cyclone V SoC which features an integrated dual core ARM processor as a host.

* Real-time Object Detection and Recognition: This demonstration shows the utility of FPGAs to efficiently run complex algorithms. Altera will show two real-time object detection and recognition systems running convolutional neural network algorithms to perform object detection and recognition on a Stratix V FPGA.

* Rapid Prototyping Flow: This hands-on demonstration features the industry’s only OpenCL-conformant solution for FPGAs. The solution provides software programmers a software development flow to write OpenCL code targeting an FPGA accelerator. The Altera SDK for OpenCL abstracts away the traditional FPGA development environment and allows users to prototype an FPGA in minutes.