Xilinx tapes out 20nm UltraScale ASIC-class programmable architecture

SAN JOSE, USA & BANGALORE, INDIA: Xilinx Inc. has taped-out the first 20nm All Programmable Device with first UltraScale ASIC-class programmable architecture. This is said to be the semiconductor industry's first 20nm device, and the PLD industry's first 20nm All Programmable device. Xilinx implemented the industry's first ASIC-class programmable architecture called UltraScale.

These milestones expand on Xilinx's industry first 28nm tape-out, All Programmable SoCs, All Programmable 3D ICs, and SoC-strength design suite. Xilinx already has several firsts in the 28nm space, such as:

* First 28nm tape-out.

* First All Programmable SoC.

* First All Programmable 3D IC.

* First SoC-strength design suite.

Neeraj Varma, director-Sales, India, said that Xilinx's global market share in the 28nm portfolio was 65 percent in March 2013. With the launch of the industry's first 20nm All Programmable Device with first UltraScale ASIC-class programmable architecture, there are improvements such as 1.5-2x performance and integration, and a year ahead of the competition. It handles massive I/O bandwidth, massive memory bandwidth, massive data flow and routing, and fastest DSP processing. The architecture will scale -- from monolithic to 3D IC, planar to FinFET, and ASIC-class performance.

The UltraSCALE architecture points to high performance smarter systems. For example, 1Tps in OTN networking, 8K in digital video, LTE-A in wireless communications, and digital array in radar. There will be requirements for massive packet processing over 400 Gbps wire-speed, massive data flow over 5Tbps, as well as massive I/O and memory bandwidth over 5Tbps, and DSP performance over 7 TMACs.

The mandate for ASIC-class programmable architecture is to remove bottlenecks for massive data flow and smart processing, high throughput with low latency, and efficient design closure with greater than 90 percent utilization without performance degradation. These are the benefits of applying leading edge ASIC techniques in a fully programmable architecture.

ASIC-like clocking maximizes performance margin for highest throughput. UltraSCALE ASIC-like clocking enables clock placement virtually anywhere on the die, making the clock skew problem go away. Also, highly optimized critical paths remove bottlenecks in DSP and packet processing. There is greatly enhanced DSP processing, high-speed memory cascading, and hardened IP for I/O intensive functions.

Next generation power management features also enable a leap in performance. The process node is up to 35 percent static at 20nm. There are more buffers for granular or coarse clock gating. Block RAM is dynamic power gating, hardened cascading. For transceivers, there are architectural optimizations. There is efficient packing and utilization of the logic fabric. For DSP, there are wider multipliers and fewer blocks per function. As for memory, there is DDR4, which operates at 1.2v vs.1.5v, voltage scaling.

Looking at the UltraScale ASIC-class architectural elements, there is massive data flow, optimized for wide buses supporting multi-terabit throughput with lowest latency. There are highly optimized critical paths, with built-in high-speed memory cascading to remove bottlenecks in DSP and packet processing. The enhanced DSP sub-systems combine critical path optimization with new 27x18-bit multipliers and dual adders that enable a massive jump in fixed- and IEEE Std 754 floating-point arithmetic performance and efficiency.

For 3D IC inter-die bandwidth, there is step function in inter-die bandwidth for 2nd generation 3D IC systems integration and new 3D IC wide memory optimized interface. For massive I/O and memory bandwidth, there is support for next generation memory interfacing with dramatic reduction in latency, optimized with multiple hardened, ASIC-class 10/100G Ethernet, Interlaken, and PCIe IP cores. There is multi-region ASIC-like clocking, delivering low-power clock networks with extremely low clock skew and high-performance scalability.

For power management, there is significant scope of static and dynamic power gating across a wide range of functional elements, yielding significant power savings. As for next generation security, with advanced approaches to AES bitstream decryption and authentication, there are key-obfuscation, and secure device programming. Finally, elimination of routing congestion leads to co-optimization with Vivado tools for greater than 90 percent device utilization without degradation in performance or latency.

The Xilinx KINTEX UltraSCALE will power 4x4 mixed-mode radios, 100G traffic manager NICs, super high-vision processing, 256-channel ultrasound and 48-channel T/R radar processing. The Xilinx VIRTEX UltraSCALE will power 400G OTN switching, 400G transponder, 400G MAC-to-Interlaken bridge, 2x100G muxponder and ASIC prototyping.

Xilinx worked with TSMC to infuse high-end FPGA requirements into the TSMC 20SoC development process, just as it had done in the development of 28HPL. The Xilinx Vivado Design Suite early access supporting UltraScale architecture-based FPGAs is now available. Initial UltraScale devices will be available in Q4-2013.